EPM7160SLC84-6 vs EPM7160SLC84-10 比較
詳細並排比較 EPM7160SLC84-6 由 Intel 與 EPM7160SLC84-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160SLC84-6 | EPM7160SLC84-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | EE PLD (CPLD) | — |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) | 4 |
| Usable Gates | 3.2K | 3,200 |
| User I/O Pins | 36 (also reported as 64 depending on source) | — |
| Pin-to-Pin Delay (tPD) | 6 ns (speed grade -6) | — |
| Counter Frequency (fCNT) | 149.3 MHz | — |
| 供應電壓 | 4.75 V to 5.25 V (single 5 V supply) | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | Yes (IEEE 1149.1 JTAG, 5.0 V) |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| MultiVolt I/O | Yes (mixed-voltage interface) | — |
| 封裝 | 84-pin PLCC (29.31 x 29.31 mm) | 84-Pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount (J-Lead) | Surface Mount |
| 工作溫度 | [DATA_NEEDED: commercial vs industrial grade] | 0C to +70C (Commercial) |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Maximum User I/O Pins | — | 64 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | EEPROM-based CMOS |
| JTAG Boundary Scan | — | Yes (IEEE Std. 1149.1 compliant) |