EPM7160SQC160-6 vs EPM7160EQC160-12 比較
詳細並排比較 EPM7160SQC160-6 由 Altera 與 EPM7160EQC160-12 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 Obsolete規格比較
| 參數 | EPM7160SQC160-6 | EPM7160EQC160-12 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Series | MAX 7000S | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | In System Programmable (ISP), EEPROM-based | — |
| Number of Macrocells | 160 | — |
| Number of Logic Elements/Blocks | 10 LABs (Logic Array Blocks) | — |
| Number of Usable Gates | 3,200 | — |
| Number of I/O Pins | 104 | — |
| Propagation Delay (tpd) | 6 ns (max, pin-to-pin) | — |
| Maximum Internal Frequency | 167 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (nominal 5 V) | 5.0 V |
| Logic Family | CMOS, TTL-compatible I/O | — |
| 工作溫度 | 0 C to 70 C (commercial) | 0 °C to +70 °C (Commercial) |
| Program/Erase Endurance | 100 cycles (EEPROM) | — |
| JTAG / Boundary Scan | IEEE Std 1149.1 compliant | — |
| 封裝 | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body | PQFP-160 (EQC), Gull-Wing |
| 安裝類型 | Surface Mount | Surface Mount |
| Dedicated Input Pins | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) | — |
| Family | — | MAX 7000E |
| Macrocells | — | 160 |
| Logic Array Blocks (LABs) | — | 4 |
| Usable Gates | — | 3,200 |
| User I/O Pins | — | 104 |
| Pin-to-Pin Logic Delay (tPD) | — | 12 ns |
| I/O Voltage | — | 5.0 V |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| Non-volatile Configuration | — | EEPROM |
| Global Clocks | — | 4 |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |