EPM7160STC100-10F vs EPM7160STC100-10 比較
詳細並排比較 EPM7160STC100-10F 由 Intel 與 EPM7160STC100-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel
EPM7160STC100-10 ⚠ 最後購買機會規格比較
| 參數 | EPM7160STC100-10F | EPM7160STC100-10 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 160 | — |
| Usable Gates | 3,200 | 3,200 |
| Maximum User I/O Pins | 84 | — |
| Dedicated Inputs | 4 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Process Technology | CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | — |
| 封裝 | 100-pin TQFP (1.0 mm height, lead-free) | 100-pin TQFP |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 °C to +70 °C (commercial) | 0 C to +70 C (commercial) |
| RoHS 狀態 | Lead-free (suffix F indicates Pb-free) | Non-RoHS (legacy Altera part; -10N variant is RoHS) |
| Macro Cells | — | 160 |
| User I/Os | — | 84 |
| Logic Elements | — | 160 macrocells / 10 Logic Array Blocks |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V - 5.25 V) |
| Propagation Delay (tPD1) | — | 10 ns |
| Global Clock Setup Time | — | 6 ns |
| Internal Counter Frequency | — | 100 MHz |
| Technology | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |