EPM7192SQC160-10 vs EPM7192SQI160-10N 比較
詳細並排比較 EPM7192SQC160-10 由 Altera 與 EPM7192SQI160-10N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 Nrnd規格比較
| 參數 | EPM7192SQC160-10 | EPM7192SQI160-10N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 7000S | MAX 7000 |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 124 | 124 |
| Usable Gates | 3750 | 3.75K (typical) |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (5V ISP, JTAG) |
| 封裝 | PQFP-160 (SQC) 28x28 mm | PQFP-160 (QFP-160, plastic) |
| Pin/Package Type | Surface Mount, Gull-Wing | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (per lead-free PQFP package marking) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Series | — | MAX 7000S |
| Architecture | — | Second-generation MAX (CMOS, EEPROM) |
| Logic Elements / Macrocells | — | 192 macrocells |
| 腳位數 | — | 160 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 167 MHz |
| Supply Voltage (VCCIO) | — | 5.0 V |
| Boundary-Scan Support | — | IEEE 1149.1 (JTAG) |
| 工作溫度 | — | 0C to +70C (industrial, 'N' suffix) |
| 安裝類型 | — | Surface Mount |
| Technology | — | 5V CMOS, EEPROM configuration memory |
| Logic Family | — | CMOS |
| Propagation Delay | — | 7.5 ns to 10 ns (speed grade dependent) |