EPM7256AETC100-5C vs EPM7256AETC100-10N 比較

詳細並排比較 EPM7256AETC100-5C 由 Altera 與 EPM7256AETC100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM7256AETC100-5C EPM7256AETC100-10N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Product Family MAX 7000A —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 256 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O 84 —
Usable Gates (typical) 6400 —
Propagation Delay (tPD) 5 ns —
Maximum Counter Frequency (fCNT) 200 MHz —
封裝 TQFP-100 100-pin TQFP
安裝類型 Surface Mount Surface Mount
Supply Voltage (VCCINT) 3.0 V to 3.6 V —
I/O Voltage (MultiVolt) 2.5 V / 3.3 V / 5.0 V compatible —
Programming Technology EEPROM (in-system programmable via JTAG) —
JTAG Support IEEE Std. 1149.1 boundary-scan —
工作溫度 0 °C to +70 °C (commercial) —
RoHS 狀態 Non-compliant (Pb-bearing TQFP package) [DATA_NEEDED: not confirmed in provided data]
Lead-Free No —
Family — MAX 7000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 256
Usable Gates — 5,000
Maximum User I/Os — 84
Logic Elements / LABs — 16 Logic Array Blocks
Pin-to-Pin Logic Delay — 10 ns
Maximum Operating Frequency — 125 MHz
Supply Voltage (Core) — 3.3 V
MultiVolt I/O Support — 2.5 V / 3.3 V / 5.0 V
Programmability — EEPROM, in-system via JTAG (IEEE 1149.1)
工作溫度範圍 — 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet]
Process Technology — 0.30 µm EEPROM
Dedicated Inputs — 4 (global clock / clear / OE)
Lead-Free / Pb-Free — [DATA_NEEDED: not confirmed in provided data]

資料表與資源

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