EPM7256AETC144-7N vs EPM7256ATI144-10 比較
詳細並排比較 EPM7256AETC144-7N 由 Intel 與 EPM7256ATI144-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7256AETC144-7N | EPM7256ATI144-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 7000A | — |
| Programmable Type | In System Programmable (EEPROM) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements / Blocks (LABs) | 16 | — |
| Number of Usable Gates | 5,000 | — |
| Number of I/O | 120 (max user I/O) | — |
| Propagation Delay tpd(1) Max | 7.5 ns | — |
| Maximum Counter Frequency | 126.6 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V | — |
| 工作溫度 | 0 °C to 70 °C (Commercial) | — |
| 封裝 / 外殼 | 144-LQFP (TQFP-144, 20x20 mm) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| RoHS 狀態 | Compliant | Non-compliant (legacy Altera marking) |
| Family | — | MAX 7000A |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Usable Gates | — | 5,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 93.5 MHz |
| User I/O Pins | — | 100 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V or 3.3 V |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| 封裝 | — | 144-pin TQFP |
| 工作溫度範圍 | — | -40C to +85C (Industrial) |
| Process Technology | — | EEPROM-based CMOS |