EPM7256EGC192-12 vs EPM7256EGC192-12EM 比較
詳細並排比較 EPM7256EGC192-12 由 Intel 與 EPM7256EGC192-12EM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM7256EGC192-12EM - MAX 7000 CPLD 256 Macro 12ns 192-Pin PGA | Intel / Altera
EPM7256EGC192-12EM ⚠ 最後購買機會規格比較
| 參數 | EPM7256EGC192-12 | EPM7256EGC192-12EM |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | MAX 7000 | MAX 7000 |
| Device Logic Cells | 256 macrocells | — |
| Usable Gates | 5,000 | 5,000 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 90.9 MHz | 90.9 MHz |
| User I/O Pins | 164 | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| 封裝 | 192-pin CPGA (Ceramic Pin Grid Array) | 192-pin CPGA (Ceramic Pin Grid Array) |
| 安裝類型 | Through Hole (PGA socket) | — |
| Technology | CMOS, EEPROM-based | — |
| 工作溫度 | 0C to +70C (commercial) | — |
| Programmable Interface | JTAG (IEEE 1149.1) / ISP | — |
| Logic Blocks (LABs) | 16 | — |
| Macrocells per LAB | 16 | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS compliant or non-compliant] |
| Lead-Free | Yes | — |
| JEDEC Package Code | S-CPGA-P192 | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/Os | — | 164 |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| I/O Voltage (MultiVolt) | — | 3.3 V or 5 V |
| Process Technology | — | EEPROM (non-volatile) |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Speed Grade | — | -12 |
| 工作溫度範圍 | — | [DATA_NEEDED: commercial or industrial temp grade] |