EPM7512BQC208-10 vs EPM7512BQC208-7 比較
詳細並排比較 EPM7512BQC208-10 由 Altera 與 EPM7512BQC208-7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7512BQC208-10 - 512-Macrocell MAX 7000B CPLD, 10ns, PQFP-208 | Altera (Intel)
EPM7512BQC208-10 Nrnd規格比較
| 參數 | EPM7512BQC208-10 | EPM7512BQC208-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000B | MAX 7000B |
| Series | MAX 7000B | — |
| Macrocells | 512 | 512 |
| Logic Elements / Blocks | 32 LABs (16 macrocells per LAB) | — |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 176 | — |
| Propagation Delay (tpd) | 10 ns (max, pin-to-pin) | — |
| Programmable Type | In-System Programmable (EEPROM) | In-System Programmable (ISP), EEPROM-based |
| Internal Supply Voltage | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to 90C (commercial) |
| 封裝 / 外殼 | 208-pin PQFP (28x28 mm), S-PQFP-G208 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Architecture | CMOS, Multiple Array Matrix (MAX) second-generation | — |
| JTAG / Boundary Scan | IEEE Std 1149.1 compliant | — |
| MSL 等級 | [DATA_NEEDED: MSL Level] | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status] |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | — | 176 |
| Maximum Internal Frequency | — | 90.1 MHz |
| Propagation Delay (tPD) | — | 7 ns |
| Supply Voltage (Core) | — | 2.375 V to 2.625 V (2.5 V nominal) |
| 封裝 | — | 208-pin PQFP (28x28 mm) |
| Package Code | — | FQFP |
| Terminal Form | — | Gull Wing |
| Logic Family | — | CMOS |
| ECCN | — | 3A991 |
| Configuration Retention | — | Non-volatile (no external configuration device required) |