EPM9320ALC84-10N vs EPM9320ALI84-10N 比較
詳細並排比較 EPM9320ALC84-10N 由 Intel 與 EPM9320ALI84-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320ALC84-10N | EPM9320ALI84-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 9000A | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 320 | — |
| Number of Gates | 6,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 60 | 56 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fCNT) | 144.9 MHz | — |
| Supply Voltage (VCC) | 5.0 V nominal | — |
| 工作溫度範圍 | 0C to +70C (Commercial) | — |
| Programmable Technology | EEPROM (in-system programmable) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| 封裝 | 84-Pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| 安裝類型 | Through-Hole / Socket | Surface Mount (PLCC socket compatible) |
| Part Status | Obsolete | — |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | — | CMOS EEPROM |
| Usable Gates | — | 6,000 to 12,000 |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| 工作溫度 | — | -40C to +85C (industrial) |
| Configuration Memory | — | EEPROM, non-volatile |