EPM9320RC208-15 vs EPM9320RC208-20N 比較
詳細並排比較 EPM9320RC208-15 由 Altera 與 EPM9320RC208-20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RC208-15 | EPM9320RC208-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Macro Cells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| 最大時脈頻率 | 117.6 MHz | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 | — |
| 封裝 | 208-pin RQFP (Power QFP) | 208-pin RQFP (PowerQuad II) |
| Package Type | 208-BFQFP Exposed Pad | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | 20 |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| 生命週期狀態 | Obsolete (PDN0706, 2007) | — |
| Logic Type | — | Complex Programmable Logic Device (CPLD) |
| Maximum Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Configuration Memory | — | EEPROM (non-volatile) |
| User I/O Pins | — | 168 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |