EPM9320RI208-10N vs EPM9320RC208-15N 比較
詳細並排比較 EPM9320RI208-10N 由 Altera 與 EPM9320RC208-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RI208-10N | EPM9320RC208-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | Complex Programmable Logic Device (CPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| 供應電壓 | 5 V | 5.0 V |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | — |
| 封裝 | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (PowerQuad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG/ISP) | Yes, via IEEE Std. 1149.1 JTAG |
| 工作溫度範圍 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| RoHS 狀態 | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Lead Finish | Lead-free (matte tin) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Propagation Delay (tPD) | — | 15 ns |
| 最大時脈頻率 | — | 117.6 MHz |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Technology | — | CMOS EEPROM (non-volatile) |
| Terminal Pitch | — | 0.5 mm |
| Packaging | — | Tray |