EPM9560GC280-20 vs EPM9560GI280-15 比較
詳細並排比較 EPM9560GC280-20 由 Altera 與 EPM9560GI280-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560GC280-20 | EPM9560GI280-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | 560 |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| 封裝 | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin PGA (ceramic, metal-sealed cofired) |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | -40 °C to 85 °C (industrial) |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| 安裝類型 | Through-Hole (CPGA socket) | — |
| RoHS 狀態 | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 |
| Architecture | — | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) |
| Flip-Flops | — | 772 |
| User I/Os | — | 216 |
| Dedicated Inputs | — | 12 |
| Logic Elements / Gates | — | 12,000 usable gates |
| Internal Frequency (fMAX) | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns |
| Clock-to-Output (tCO) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 4.5 V to 5.5 V (3.3 V or 5 V I/O) |
| In-System Programmability | — | 5.0-V ISP via JTAG |
| 濕度敏感等級 (MSL) | — | MSL-3 (168 hours) |