EPM9560RC208-10N vs EPM9560RC-10 比較
詳細並排比較 EPM9560RC208-10N 由 Intel 與 EPM9560RC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-10N | EPM9560RC-10 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay (tPD1) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Bank Voltage (VCCIO) | 5.0 V | — |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | 240-pin PGA (RC suffix) |
| 安裝類型 | Surface Mount | Through-Hole / Socketed |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programmability | — | IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array Matrix (MAX) - third generation |