EPM9560RC208-15 vs EPM9480RC208-15 比較
詳細並排比較 EPM9560RC208-15 由 Altera 與 EPM9480RC208-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-15 | EPM9480RC208-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 10,000 gates |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Speed | 117.6 MHz | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | RQFP-208 |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -15 (15 ns pin-to-pin) | — |
| Architecture | Third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - 3rd generation |
| Logic Cells / Macro Cells | — | 480 macro cells |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tPD) | — | 15 ns |
| User I/O Pins | — | 153 |
| Programmability | — | In-System (ISP) via JTAG IEEE 1149.1 |
| Configuration Memory | — | EEPROM (non-volatile) |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |