EPM9560RC208-15C vs EPM9560RC208-15N 比較
詳細並排比較 EPM9560RC208-15C 由 Altera 與 EPM9560RC208-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-15C | EPM9560RC208-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based CPLD (EPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Counter Frequency | 117.6 MHz | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Memory | EEPROM (non-volatile) | CMOS EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封裝 | 208-pin RQFP | 208-pin RQFP (Power Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | 0C to +70C (commercial) | — |
| Speed Grade | -15 (15 ns) | -15 (15 ns tPD) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] |
| Logic Architecture | Multiple Array MatriX (MAX) third generation | — |
| Series | — | MAX 9000 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O | — | 212 (in 208-RQFP, see family datasheet) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Operating Temperature (commercial) | — | 0C to +70C |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |