EPM9560RC208-15N vs EPM9560RC208-13 比較
詳細並排比較 EPM9560RC208-15N 由 Intel 與 EPM9560RC208-13 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-15N | EPM9560RC208-13 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | 20 |
| User I/O | 212 (in 208-RQFP, see family datasheet) | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Configuration Memory | CMOS EEPROM (non-volatile) | — |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature (commercial) | 0C to +70C | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns tPD) | -13 (13 ns pin-to-pin) |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Device Family | — | MAX 9000 EPLD |
| User I/O Pins | — | 208 |
| Package Code | — | RC208 |
| Propagation Delay (tPD) | — | 13 ns |
| 最大時脈頻率 | — | 125 MHz |
| 供應電壓 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Programming Interface | — | IEEE 1149.1 JTAG |
| 工作溫度範圍 | — | 0C to +70C (commercial) |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |