EPM9560RC208-15N vs EPM9560RC208-19 比較
詳細並排比較 EPM9560RC208-15N 由 Intel 與 EPM9560RC208-19 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-15N | EPM9560RC208-19 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| User I/O | 212 (in 208-RQFP, see family datasheet) | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Configuration Memory | CMOS EEPROM (non-volatile) | — |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | RQFP-208 (208-pin PQFP) |
| Operating Temperature (commercial) | 0C to +70C | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] | [DATA_NEEDED: RoHS status] |
| Speed Grade | -15 (15 ns tPD) | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Flip-Flops | — | 772 |
| User I/O Pins | — | 149 |
| Propagation Delay (tPD) | — | 19 ns |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |
| I/O Voltage Tolerance | — | 3.3 V / 5 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Technology | — | CMOS EEPROM |
| JEDEC Package Code | — | S-PQFP-G208 |
| 工作溫度 | — | [DATA_NEEDED: operating temperature grade] |