EPM9560RC208-17 vs EPM9560RC208-15N 比較
詳細並排比較 EPM9560RC208-17 由 Altera 與 EPM9560RC208-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-17 | EPM9560RC208-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | MAX 9000 | — |
| Product Type | CPLD (EPLD, in-system programmable) | — |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Pin-to-Pin Delay (tPD) | 17 ns | 15 ns |
| Maximum Counter Frequency | 117.6 MHz | — |
| User I/O Pins | 212 | — |
| Supply Voltage (VCC) | 5 V | — |
| 封裝 | 208-pin RQFP (RC208) | 208-pin RQFP (Power Quad Flat Pack) |
| Programming Technology | EEPROM (in-system programmable) | — |
| Program/Erase Cycles | 100 minimum | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Architecture | Third-generation MAX (AND-OR PLA) | Multiple Array MatriX (MAX) - third generation |
| 安裝類型 | Surface Mount | Surface Mount |
| Series | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| User I/O | — | 212 (in 208-RQFP, see family datasheet) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | — | CMOS EEPROM (non-volatile) |
| Operating Temperature (commercial) | — | 0C to +70C |
| RoHS 狀態 | — | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] |
| Speed Grade | — | -15 (15 ns tPD) |