EPM9560RC208-4C vs EPM9560RC208-10 比較

詳細並排比較 EPM9560RC208-4C 由 Altera 與 EPM9560RC208-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM9560RC208-4C EPM9560RC208-10
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family MAX 9000 (EPM9560) —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 12 16
Maximum User I/O Pins 164 212 (208-pin package variant)
封裝 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Plastic Quad Flat Pack)
Speed Grade -4 (12 ns pin-to-pin) —
供應電壓 5.0 V —
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes (JTAG ISP) —
工作溫度範圍 0C to +70C (commercial) —
安裝類型 Surface Mount Surface Mount
Pin-to-Pin Delay 12 ns —
Maximum System Frequency 125 MHz —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: not stated in retrieved distributor listings]
MSL 等級 [DATA_NEEDED: MSL level] —
Manufacturer Altera Corporation —
Family — MAX 9000
Device Type — CPLD (Complex Programmable Logic Device)
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: internal toggle frequency in MHz]
Supply Voltage (VCCINT) — 5.0 V
I/O Standards Supported — 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O)
Configuration Memory — EEPROM (in-system programmable via JTAG)
Process Technology — 0.30 µm CMOS EEPROM
工作溫度 — 0C to +70C (commercial)
Lead-Free — [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing]
Programmability — JTAG (IEEE 1149.1) in-system programming

資料表與資源

瀏覽所有產品 建立 BOM 索取報價