EPM9560RC240-12 vs EPM9560RC240-10N 比較
詳細並排比較 EPM9560RC240-12 由 Altera 與 EPM9560RC240-10N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ 最後購買機會規格比較
| 參數 | EPM9560RC240-12 | EPM9560RC240-10N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | MAX 9000 (EPM9560) | MAX 9000 |
| Device Type | EE PLD / CPLD | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| User I/O Pins | 191 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Maximum Propagation Delay (tPD) | 13.4 ns | — |
| Speed Grade | -12 (13.4 ns tPD) | — |
| Maximum Operating Frequency (estimated) | ~76 MHz registered | — |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Logic Levels | 3.3 V or 5 V (configurable) | — |
| 封裝 | PQFP-240 (RC240) 0.500 mm pitch, gull-wing | 240-pin RQFP (Plastic Quad Flat Pack) |
| 安裝類型 | Surface Mount | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | IEEE 1149.1 JTAG | JTAG (IEEE 1149.1) - in-system programmable |
| Process Technology | CMOS | 0.65 µm CMOS EEPROM |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | ROHS3 Compliant (per fpgalink.com listing) |
| Architecture | — | Multiple Array MatriX (MAX) - 3rd generation |
| Usable Gates | — | 12,000 |
| User I/Os | — | 212 |
| Internal Operating Frequency | — | 144.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| 供應電壓 | — | 5.0 V |
| I/O Standards Supported | — | 5.0 V TTL/CMOS, 3.3 V PCI-compatible |
| Operating Temperature (Commercial) | — | 0 °C to +70 °C |
| Lead-Free Finish (N suffix) | — | Yes (Pb-free) |
| 濕度敏感等級 (MSL) | — | 3 (168 hours) |