EPM9560RC304-15 vs EPM9560RC-304 比較
詳細並排比較 EPM9560RC304-15 由 Altera 與 EPM9560RC-304 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC304-15 | EPM9560RC-304 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 | — |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 35 |
| User I/O Pins | 212 (maximum) | 216 |
| Propagation Delay (tPD) | 15 ns (combinatorial, pin-to-pin) | — |
| 腳位數 | 304 | — |
| 封裝 | 304-pin RQFP (Plastic Quad Flat Pack) | 304-pin RQFP / PQFP-G304 |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| I/O Standard | 5.0 V TTL / PCI-compliant | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Technology Node | High-performance CMOS, EEPROM process | — |
| 工作溫度 | [DATA_NEEDED: industrial/commercial temperature grade] | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: lead-free / RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 12,000 |
| Flip-Flops | — | 772 |
| JEDEC Package Code | — | S-PQFP-G304 |
| Process Technology | — | CMOS EEPROM |
| MultiVolt I/O Support | — | 3.3 V / 5 V |
| Maximum Frequency (-15 grade) | — | 117.6 MHz |
| Propagation Delay (-12 grade) | — | 13.4 ns |
| Propagation Delay (-15 grade) | — | 15 ns |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature (Commercial) | — | 0C to +70C |