EPM9560RC304-15 vs EPM9560RC304-5 比較

詳細並排比較 EPM9560RC304-15 由 Altera 與 EPM9560RC304-5 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM9560RC304-15 EPM9560RC304-5
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family MAX 9000 MAX 9000 (EPM9560)
Architecture Multiple Array MatriX (MAX), EEPROM-based —
Macrocells 560 560
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
User I/O Pins 212 (maximum) —
Propagation Delay (tPD) 15 ns (combinatorial, pin-to-pin) [DATA_NEEDED: propagation delay]
腳位數 304 —
封裝 304-pin RQFP (Plastic Quad Flat Pack) 304-pin RQFP (PowerQuad II)
Supply Voltage (VCCINT) 5.0 V —
I/O Standard 5.0 V TTL / PCI-compliant —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes (JTAG ISP)
Configuration Memory On-chip EEPROM (non-volatile) —
Technology Node High-performance CMOS, EEPROM process —
工作溫度 [DATA_NEEDED: industrial/commercial temperature grade] —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: lead-free / RoHS compliance status] ROHS3 Compliant
Device Type — Complex Programmable Logic Device (CPLD) / EPLD
Usable Gates — 12,000
Maximum Operating Frequency — 117.6 MHz (family -15 grade reference)
供應電壓 — 5.0 V
Speed Grade — -5 (fastest grade in family)
Configuration Technology — EEPROM (non-volatile)
濕度敏感等級 (MSL) — 3 (168 Hours)
Manufacturer Standard Lead Time — 1-7 Days (distributor listing)
工作溫度範圍 — [DATA_NEEDED: operating temperature range]
Number of I/O Pins — [DATA_NEEDED: number of user I/O pins]

資料表與資源

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