EPM9560RC304-5 vs EPM9560RC30415 比較
詳細並排比較 EPM9560RC304-5 由 Altera 與 EPM9560RC30415 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC304-5 | EPM9560RC30415 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | — |
| Device Type | Complex Programmable Logic Device (CPLD) / EPLD | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Speed Grade | -5 (fastest grade in family) | -15 (15 ns pin-to-pin delay) |
| 封裝 | 304-pin RQFP (PowerQuad II) | 304-RQFP (Power Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | Yes (IEEE 1149.1 JTAG) |
| 濕度敏感等級 (MSL) | 3 (168 Hours) | — |
| RoHS 狀態 | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Manufacturer Standard Lead Time | 1-7 Days (distributor listing) | — |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: propagation delay] | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: number of LABs] | 16 (40 macro cells each) |
| Family | — | MAX 9000 |
| Architecture | — | Multiple Array MatriX (MAX), EEPROM-based |
| Macro Cells | — | 560 |
| User I/O Pins | — | 360 |
| 腳位數 | — | 304 |
| Maximum Internal Frequency | — | 117.6 MHz |
| Technology | — | CMOS EEPROM |