EPM9560RC340-15 vs EPM9560RC304-10 比較
詳細並排比較 EPM9560RC340-15 由 Altera 與 EPM9560RC304-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC340-15 | EPM9560RC304-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD / EPLD |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 16000 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| User I/O Pins | 212 | 304 (package-limited) |
| 封裝 | 340-RQFP (Reduced Quad Flat Pack) | RQFP-304 (RC) |
| 安裝類型 | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | 0.65 µm CMOS EEPROM |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Boundary Scan | IEEE Std. 1149.1 JTAG | — |
| Programming Technology | EEPROM (non-volatile, reprogrammable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - not explicitly stated in verified data] | ROHS3 Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 560 |
| 腳位數 | — | 304 |
| Pin-to-Pin Propagation Delay | — | 12 ns |
| Speed Grade | — | -10 |
| 供應電壓 | — | 5 V |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Method | — | JTAG in-system (ISP) |
| MSL 等級 | — | 3 (168 Hours) |