EPM9560SRC240-15 vs EPM9560RI240-15N 比較
詳細並排比較 EPM9560SRC240-15 由 Altera 與 EPM9560RI240-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560SRC240-15 | EPM9560RI240-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 9000 | — |
| Device Type | EPLD / CPLD (Complex Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 560 | 12,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Macrocells | 212 | 560 |
| Maximum User I/O Pins | [DATA_NEEDED: exact I/O count for SRC240 package] | — |
| Speed Grade | -15 (15 ns tPD) | — |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (max) | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Programmability | In-system programmable via IEEE 1149.1 JTAG | — |
| Non-volatile | Yes (EPROM/EEPROM cells) | — |
| 封裝 | RQFP-240 (Surface Mount) | 240-pin RQFP (PowerQuad Flat Pack) |
| 工作溫度 | [DATA_NEEDED: commercial 0-70C or industrial -40-85C] | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not stated in provided data] | RoHS3 Compliant |
| Process Technology | CMOS EPROM | — |
| Logic Family | — | MAX 9000 (Multiple Array MatriX) |
| Flip-Flops | — | 772 |
| User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Internal Frequency | — | 145 MHz |
| 供應電壓 | — | 5.0 V |
| I/O Voltage Compatibility | — | 3.3 V or 5.0 V configurable |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE 1149.1 (JTAG) boundary scan |
| 工作溫度範圍 | — | -40 C to +85 C (industrial) |
| Moisture Sensitivity Level | — | MSL 3 (168 hours) |
| Manufacturer Standard Lead Time | — | 1-7 days (distributor stock) |