P5010NSN1TNB vs P5020NSN1TNB 比較

詳細並排比較 P5010NSN1TNB 由 NXP Semiconductors 與 P5020NSN1TNB 由 NXP Semiconductors. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

NXP Semiconductors
P5010NSN1TNB P5010NSN1TNB - QorIQ P5 64-Bit e5500 MPU 2.0GHz | NXP

P5010NSN1TNB - QorIQ P5 64-Bit e5500 MPU 2.0GHz | NXP

P5010NSN1TNB ✓ 啟用中
NXP Semiconductors
P5020NSN1TNB P5020NSN1TNB - QorIQ P5020 Dual-Core 1.8GHz SoC | NXP | Networking

P5020NSN1TNB - QorIQ P5020 Dual-Core 1.8GHz SoC | NXP | Networking

P5020NSN1TNB ✓ 啟用中

規格比較

參數 P5010NSN1TNB P5020NSN1TNB
品牌 NXP Semiconductors NXP Semiconductors
類別 Microcontrollers Microcontrollers
生命週期狀態 啟用中 啟用中
Core Architecture Power Architecture e5500 —
Number of Cores 1 —
資料匯流排寬度 64-bit —
Maximum Core Frequency 2.0 GHz 2.0 GHz (per DigiKey listing); 1.8 GHz per Mouser/Freescale spec
Series QorIQ P5 —
Memory Controller DDR3 / DDR3L up to 1866 MT/s —
Ethernet 10 Gigabit + Multiple 1 GbE MACs —
PCI Express PCIe Gen 2 —
Serial RapidIO Yes —
Hardware Acceleration Pattern matching, security / encryption offload DPAA (Data Path Acceleration Architecture) for packet/crypto offload
工作溫度 0 C to +105 C 0C to +105C
封裝 1295-ball FCBGA (37.5 x 37.5 mm) 1295-FCPBGA (37.5 mm x 37.5 mm)
安裝類型 Surface Mount (BGA) Surface Mount (FCBGA ball grid)
RoHS 狀態 [DATA_NEEDED: rohs status not in provided data] Compliant
Encryption Integrated hardware crypto accelerator —
Architecture — PowerPC e5500 64-bit dual-core
Core Count — 2 (dual-core)
Memory Interface — DDR3 / DDR3L with ECC
PCIe Controllers — Multiple lanes (Gen2/Gen3 capable)
Ethernet Interfaces — Gigabit Ethernet (multiple MACs)
Serial RapidIO (sRIO) — Yes
Encryption Variant — No ('N' indicator in suffix)
MSL (Moisture Sensitivity Level) — [DATA_NEEDED: MSL level]
Reach Status — Compliant
Junction Temperature (Tj max) — [DATA_NEEDED: junction temperature maximum]
Process Node — [DATA_NEEDED: process technology node]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價