RTAX1000SL-1CGS624E vs RTAX1000SL-1CGS624B 比較
詳細並排比較 RTAX1000SL-1CGS624E 由 Microchip Technology 與 RTAX1000SL-1CGS624B 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX1000SL-1CGS624E - 1M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX1000SL-1CGS624E ✓ 啟用中Microchip Technology
RTAX1000SL-1CGS624B - Rad-Tolerant FPGA 1M Gates | Microchip
RTAX1000SL-1CGS624B ✓ 啟用中規格比較
| 參數 | RTAX1000SL-1CGS624E | RTAX1000SL-1CGS624B |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| System Gates | 1,000,000 | — |
| ASIC Gates (embedded) | 125,000 | — |
| Configurable Logic Blocks (CLBs) | 12096 | 12096 |
| Family | RTAX-S/SL (radiation-tolerant, antifuse) | RTAX-S/SL Radiation-Tolerant FPGA |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage | 1.5 V | — |
| Maximum System Performance | 581 MHz | — |
| 封裝 | CGA-624 (ceramic column grid array, 624 pins) | 624-ball Ceramic CGA (CGS624) |
| Speed Grade | -1 | -1 |
| 工作溫度 | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Programming Technology | Antifuse (one-time programmable, live at power-up) | Anti-fuse (one-time programmable, live at power-up) |
| SEU Immunity | SEU-hardened registers; soft-error rate < 10-10 errors/bit-day | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| 安裝類型 | Surface Mount | Surface Mount |
| Application Domain | Space flight systems | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Embedded FIFO Control | Yes | — |
| Logic Density | — | 1,000,000 equivalent system gates |
| ASIC Gates | — | 125,000 additional ASIC gates |
| Series | — | RTAX1000SL |
| Technology | — | Digital CMOS |
| Radiation Tolerance | — | Radiation-tolerant (space flight qualified) |
| Qualification | — | DLA SMD 5962-0422006QUA per MIL-PRF-38535 |
| 供應電壓 | — | [DATA_NEEDED: core/IO supply voltage] |
| Maximum User I/O | — | [DATA_NEEDED: maximum user I/O count] |
| Architecture Base | — | Derived from Microsemi commercial Axcelerator family |