RTAX1000SL-CGS624E vs RTAX2000S-1CGS624V 比較
詳細並排比較 RTAX1000SL-CGS624E 由 Microchip Technology 與 RTAX2000S-1CGS624V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX1000SL-CGS624E - 1M-Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX1000SL-CGS624E ✓ 啟用中Microchip Technology
RTAX2000S-1CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624V ✓ 啟用中規格比較
| 參數 | RTAX1000SL-CGS624E | RTAX2000S-1CGS624V |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Equivalent System Gates | 1000000 gates | 2,000,000 |
| Additional ASIC Gates | 125000 gates | — |
| Configurable Logic Blocks (CLBs) | 12096 | 21,504 |
| Maximum System Frequency | 581 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage | 1.5 V | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S Radiation-Tolerant FPGA |
| 封裝 | 624-ball Ceramic Column Grid Array (CGS624) | CG624 Ceramic Column Grid Array (CCGA), 624 balls |
| Radiation Tolerance | Radiation-tolerant (space-flight qualified family) | — |
| Configuration | Non-volatile anti-fuse, live-at-power-up, single chip | Live at power-up, single-chip (no external config device) |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking Features | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Dedicated carry logic | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: Operating Temperature] | -55C to +125C |
| I/O Count | [DATA_NEEDED: User I/O Count] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS Status] | [DATA_NEEDED: RoHS status] |
| Total Logic Cells | — | 32,256 |
| ASIC Gate Capacity (companion) | — | 250,000 gates |
| Core Supply Voltage (nominal) | — | 1.5 V |
| Core Supply Voltage Range | — | 1.425 V to 1.575 V |
| Logic Family | — | CMOS |
| Speed Grade | — | -1 |
| Programming Technology | — | Antifuse (one-time programmable) |
| SEU Hardening | — | SEU-hardened registers, immune to single-event upsets |
| Weight | — | [DATA_NEEDED: package weight] |