RTAX2000S-1CGS624EV vs RTAX1000S-1CGS624V 比較

詳細並排比較 RTAX2000S-1CGS624EV 由 Microchip Technology 與 RTAX1000S-1CGS624V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Microchip Technology
RTAX2000S-1CGS624EV RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip

RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip

RTAX2000S-1CGS624EV ✓ 啟用中
Microchip Technology
RTAX1000S-1CGS624V RTAX1000S-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000S-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000S-1CGS624V ✓ 啟用中

規格比較

參數 RTAX2000S-1CGS624EV RTAX1000S-1CGS624V
品牌 Microchip Technology Microchip Technology
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
System Gates 2,000,000 —
Logic Cells (CLBs) 21504 —
Total Cells 32256 —
Additional ASIC Equivalent Gates 250000 —
封裝 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) CGS624 (624-ball ceramic column grid array)
Core Supply Voltage 1.5 V nominal (1.425 V to 1.575 V) 1.5 V
工作溫度 -55C to +125C -55C to +125C
Process Technology 0.15 um CMOS —
Maximum Frequency 649 MHz —
Logic Family CMOS —
SEU Immunity SEU-hardened registers, immune to single-event upsets to specified LET threshold —
SEU Rate < 10-10 errors/bit-day —
Configuration One-time programmable anti-fuse, live at power-up, single chip —
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
安裝類型 Surface Mount Surface Mount
Product Family RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs —
Thermal Resistance Basis JEDEC JESD51 simulation conditions (per datasheet) —
I/O Supply Voltage [DATA_NEEDED: I/O bank voltage] —
Maximum User I/O [DATA_NEEDED: user I/O count] —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS Status]
Equivalent System Gates — 1,000,000
Dedicated Logic Cells — 18144
Cluster Logic Blocks (CLBs) — 12096
Technology — CMOS, antifuse-based
Family — RTAX-S (Radiation-Tolerant)
Programming Type — One-Time Programmable (antifuse)
Radiation Tolerance — Designed for space-flight radiation environments
Live at Power-Up — Yes (no external configuration device)
System Features — Segmentable clocks, chip-wide highway routing
Application Domain — Space-flight systems
I/O Standard Support — [DATA_NEEDED: I/O standards]

資料表與資源

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