RTAX2000SL-CGS624V vs RTAX2000S-CGS624V 比較
詳細並排比較 RTAX2000SL-CGS624V 由 Microchip Technology 與 RTAX2000S-CGS624V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ 啟用中Microchip Technology
RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip
RTAX2000S-CGS624V ✓ 啟用中規格比較
| 參數 | RTAX2000SL-CGS624V | RTAX2000S-CGS624V |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Equivalent System Gates | 2000000 | 2000000 |
| Logic Cells (CLBs) | 21504 | — |
| Technology | CMOS antifuse (nonvolatile) | Digital CMOS, anti-fuse OTP |
| User I/Os (maximum) | 684 | — |
| Embedded Memory | 540 kbits with optional EDAC protection | Embedded SRAM with built-in FIFO control logic |
| Total Ionizing Dose (TID) | 300 krad (Si) functional / 200 krad (Si) parametric | — |
| Single-Event Upset Rate | Less than 1E-10 errors per bit-day | — |
| Configuration | One-time programmable antifuse, live at power-up | — |
| Embedded SRAM Features | Built-in FIFO control logic | — |
| Clock Architecture | Segmentable clock structures | — |
| Routing | Chip-wide highway routing, carry logic | — |
| 封裝 | CG624 ceramic package | CG624 ceramic column grid array |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| Application Domain | Space-flight systems | Space-flight systems |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| System Frequency (typical) | [DATA_NEEDED: system frequency] | — |
| Configurable Logic Blocks (CLBs) | — | 21504 |
| Logic Cells | — | 32256 |
| Core Supply Voltage (Nominal) | — | 1.5 V |
| Core Supply Voltage Range | — | 1.425 V to 1.575 V |
| 安裝類型 | — | Surface Mount |
| Configuration Type | — | One-Time Programmable (anti-fuse), live at power-up |
| Clocking | — | Segmentable clocks |
| Routing Features | — | Chip-wide highway routing, carry logic |
| Max Family Density | — | 4000000 equivalent system gates (family max) |