RTAX4000DL-CQ352E vs RTAX4000DL-CQ352V 比較
詳細並排比較 RTAX4000DL-CQ352E 由 Microchip Technology 與 RTAX4000DL-CQ352V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX4000DL-CQ352E - 4M-Gate Rad-Tolerant FPGA | Microchip
RTAX4000DL-CQ352E ✓ 啟用中Microchip Technology
RTAX4000DL-CQ352V - 4M-Gate Radiation-Tolerant FPGA | Microchip
RTAX4000DL-CQ352V ✓ 啟用中規格比較
| 參數 | RTAX4000DL-CQ352E | RTAX4000DL-CQ352V |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Manufacturer | Microchip Technology (Actel/Microsemi) | — |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | RTAX-S/SL and RTAX-DSP (RTAX-DSP) |
| Equivalent System Gates | 4,000,000 gates | 4,000,000 |
| Logic Cells | 55,440 | 55,440 |
| CLBs | 36,960 | — |
| Process Technology | CMOS | CMOS, antifuse (one-time programmable) |
| Programmability | Antifuse (live-at-power-up) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| DSP Resources | Dedicated multiply-accumulate blocks (RTAX-DSP variant) | — |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Carry logic | — |
| 封裝 | CQ352 ceramic column package, 352 pins | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Application Domain | Space-flight systems | — |
| Radiation Tolerance | Radiation-tolerant (TID and SEE qualified per family datasheet) | — |
| Configuration | True single-chip form factor | Live at power up, single-chip |
| RoHS 狀態 | [DATA_NEEDED: RoHS Status] | [DATA_NEEDED: RoHS status] |
| CLB Organization | — | 36,960 CLBs |
| Core Supply Voltage | — | 1.5 V nominal |
| 工作溫度 | — | -55C to +125C |
| Package Type | — | 352-terminal S-CQFP ceramic metal-sealed cofired flatpack (CQ352) |
| Package Dimensions | — | 48 mm x 48 mm, square, with guard ring |
| JEDEC-30 Package Code | — | S-CQFP |
| Radiation Tolerance Class | — | Radiation-tolerant (space-flight) |
| Routing Features | — | Segmentable clocks, chip-wide highway routing, carry logic |
| Total User I/O | — | [DATA_NEEDED: total user I/O count] |