RTAX4000SL-1CG1272EV vs RTAX4000S-1CG1272V 比較
詳細並排比較 RTAX4000SL-1CG1272EV 由 Microchip Technology 與 RTAX4000S-1CG1272V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX4000SL-1CG1272EV - 4M-Gate Rad-Tolerant FPGA CCGA-1272 | Microchip
RTAX4000SL-1CG1272EV ✓ 啟用中Microchip Technology
RTAX4000S-1CG1272V - 4M-Gate Rad-Tolerant FPGA | Microchip
RTAX4000S-1CG1272V ✓ 啟用中規格比較
| 參數 | RTAX4000SL-1CG1272EV | RTAX4000S-1CG1272V |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | RTAX-SL (Radiation-Tolerant FPGA) | RTAX-S Radiation-Tolerant FPGA |
| System Gates | 4,000,000 equivalent system gates | — |
| Logic Cells | 40,320 | 60480 |
| Process Technology | 0.15 um CMOS | — |
| Core Supply Voltage | 1.5 V | — |
| 封裝 | 1272-Pin CCGA (Ceramic Column Grid Array) | CBGA1272 (CG1272) ceramic column grid array |
| Logic Family | CMOS | — |
| 工作溫度 | -55C to +125C | — |
| SEU Immunity | SEU rate < 10-10 errors/bit-day; SEU-hardened registers | — |
| Configuration | Live-at-power-up (antifuse, single-chip) | Live at power-up, true single-chip |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| TMR Requirement | SEU-hardened registers eliminate need for triple-module redundancy | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Application Domain | Space-flight systems | Space-flight systems (radiation-tolerant) |
| Derived From | Actel/Microsemi Axcelerator commercial family | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Radiation TID | [DATA_NEEDED: total ionizing dose rating] | — |
| CLBs (Combinatorial Logic Blocks) | — | 40320 |
| Equivalent System Gates | — | 4000000 gates |
| Supply Voltage (Nominal) | — | 1.5 V |
| Speed Grade | — | -1 |
| Terminal Pitch | — | 1.000 mm |
| Ball/Column Count | — | 1272 |
| 工作溫度範圍 | — | -55C to +125C |
| Programmability | — | One-Time Programmable (antifuse) OTP |
| Clock Architecture | — | Segmentable clocks, chip-wide highway routing |