74HCT1G04GW - Single Inverter Gate, 5-TSSOP | Nexperia
MPN： 74HCT1G04GW ✓ 啟用中74HCT1G04GW 概覽
What is a single-gate logic IC? A single-gate logic IC is a minimal-footprint logic function packaged in a small-outline surface-mount package (typically 5 to 6 pins). It belongs to the logic IC hierarchy: inverter -> gate -> combinational logic -> standard logic family. Single-gate devices occupy a single logic function on one die, enabling designers to place a single inverter, buffer, OR, AND, or Schmitt-trigger function exactly where it is needed on a board without paying the area or cost of a quad-gate or hex-gate package. Compared with discrete BJT/MOSFET inverter circuits, single-gate CMOS ICs offer matched propagation delays, balanced rise/fall times, ESD-rated inputs, and predictable output impedance across the full operating temperature range.
Key features of the 74HCT1G04 include a wide supply voltage range, symmetrical output impedance, ESD protection on every input, balanced propagation delays, and very low power dissipation. Inputs include clamp diodes that allow current-limiting resistors to interface inputs to voltages exceeding VCC, simplifying mixed-voltage designs without external protection.
Architecturally, the 74HCT1G04 uses an HCT sub-family CMOS process: the input stage accepts TTL logic levels (VIL <= 0.8 V, VIH >= 2.0 V) while the output stage swings rail-to-rail CMOS levels. This makes the HCT variant the bridge between legacy 5 V TTL peripherals and modern CMOS controllers. The standard output current is half that of the larger 74HCT04 hex inverter, but for a single logic inversion this is rarely a constraint.
Typical applications include signal inversion in microcontroller I/O lines, bus signal conditioning, level translation between 5 V and 3.3 V logic domains, reset-signal inversion, and clock-signal polarity reversal. Designers also use it to debounce mechanical switches when combined with an RC network. The 5-pin TSSOP footprint keeps the inverter within a few square millimeters of board area, ideal for high-density PCB layouts and signal-integrity sensitive traces.
When designing with this part, place a 0.1 uF decoupling capacitor as close as possible to the VCC pin, keep the input trace short to minimize capacitive loading, and verify that the driving source can supply at least 1 mA through the input clamp diode if input voltages can exceed VCC during hot-plug or fault conditions.
This page consolidates distributor pricing for the 74HCT1G04GW, 5-TSSOP drop-in alternatives from Nexperia and TI, and engineering design notes that complement the manufacturer datasheet.
直接替換替代品，適用於 74HCT1G04GW — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： 74HCT1G04GW （相同外形與佔位） — 差異在於 Logic Family, Logic Type, Package, Supply Voltage (VCC).
74HCT1G04GW-Q100H
✅ 直接替換聯絡詢價
查看資料表 →74HCT1G04GW,125
✅ 直接替換📋 參考替代品（不在目錄中）
74HC1G04GW,125
✅ 直接替換📋 參考替代品（不在目錄中）
74HCT1G04GW-G
✅ 直接替換📋 參考替代品（不在目錄中）
74HCT1G04GW/S716H
✅ 直接替換📋 參考替代品（不在目錄中）
SN74HCT1G04DCKR
✅ 直接替換📋 參考替代品（不在目錄中）
74HCT1G04GW 最大額定值與電氣特性
| Logic Type | Inverter |
| Number of Circuits | 1 |
| Number of Inputs | 1 |
| Logic Family | HCT (TTL-compatible CMOS) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| Wide Supply Voltage Range (HC version) | 2.0 V to 6.0 V |
| Input Switching Levels | TTL (VIL <= 0.8 V, VIH >= 2.0 V) |
| Output Drive Current | Standard (half of 74HCT04) |
| Propagation Delay (typ.) | 27 ns |
| 工作溫度 | -40 C to +125 C |
| 封裝 | 5-TSSOP (SOT353 / UMT5) |
| 安裝類型 | Surface Mount |
| Input Clamp Diodes | Yes |
| ESD Protection | HBM JESD22-A114E |
| RoHS 狀態 | Compliant |
74HCT1G04GW 腳位配置
| 腳位 1 | NC — Not connected (per datasheet) |
| 腳位 2 | A — Data input |
| 腳位 3 | GND — Ground (0 V) |
| 腳位 4 | Y — Data output (inverted) |
| 腳位 5 | VCC — Supply voltage (4.5 V to 5.5 V for HCT) |
典型應用
74HCT1G04GW 適用於 6 應用s: 5V TTL to 3.3V CMOS Level Translation, Microcontroller GPIO Polarity Inversion, Clock Signal Polarity Reversal, Reset Signal Conditioning, Switch Debounce with RC Network, Industrial Control Logic Glue.
5V TTL to 3.3V CMOS Level Translation
The 74HCT1G04GW is widely used as a unidirectional 5 V TTL to 3.3 V CMOS level translator. With VCC tied to the 3.3 V rail, the TTL-compatible input thresholds (VIL <= 0.8 V, VIH >= 2.0 V) accept a 5 V CMOS or TTL signal cleanly, while the rail-to-rail CMOS output drives the 3.3 V logic domain. The single 5-pin TSSOP footprint lets designers place one inverter per signal at the boundary of mixed-voltage islands, with predictable propagation delay (~27 ns typical) and minimal quiescent draw.
推薦
Microcontroller GPIO Polarity Inversion
Engineers use the 74HCT1G04GW to invert a single microcontroller GPIO line when a peripheral requires an active-low control signal but only an active-high source is available. The 5-pin TSSOP footprint fits beside QFN microcontroller footprints without consuming meaningful board area, and the CMOS output stage with input stage drives both GPIO and logic-IC loads with symmetrical rise and fall times. The TTL-compatible input is forgiving of 3.3 V GPIO drive, simplifying firmware-driven polarity inversion.
推薦
Clock Signal Polarity Reversal
The 74HCT1G04GW inverts a low-frequency clock or oscillator output when a downstream PLL, counter, or flip-flop needs the opposite edge polarity. At propagation delays of ~27 ns typical, it is best suited to clocks under 5 MHz, but works for higher frequencies when board-trace delay budgets are tight. Balanced propagation delays keep duty cycle close to 50 percent, and the low-output-impedance CMOS output stage isolates the clock source from capacitive loading.
推薦
Reset Signal Conditioning
In reset distribution networks, the 74HCT1G04GW inverts and buffers reset signals from a supervisor or push-button network, providing a single, clean, rail-to-rail CMOS reset to a microcontroller or DSP. Its TTL-compatible input accepts the open-drain output of many reset supervisors, and the symmetric CMOS output ensures a sharp, monotonic transition under heavy capacitive load. The 5-TSSOP footprint mounts directly beside the supervisor or reset button.
推薦
Switch Debounce with RC Network
A 74HCT1G04GW combined with an RC low-pass network forms a compact hardware debounce circuit for mechanical switches and panel buttons. The Schmitt-free HCT input does not have hysteresis, so the RC time constant should exceed the bounce interval (typically 5 to 10 ms). Because of its TTL-compatible thresholds, the inverter reliably rejects slow edges caused by switch bounce, providing a clean logic-level output to the host controller.
推薦
Industrial Control Logic Glue
In industrial PLC, sensor, and motor-control boards, the 74HCT1G04GW serves as glue logic to invert individual control or status lines where the surrounding logic family is 5 V TTL. Its 5-pin TSSOP package and -40 C to +125 C operating range suit harsh industrial environments, while the input clamp diodes allow safe interfacing to higher-voltage signals via series current-limiting resistors. Automotive-grade Q100 variants extend the same role into vehicle ECUs.
推薦
推薦產品摘要
工程參考資料，適用於 74HCT1G04GW — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | 74HCT1G04GW-Q100H | 74HC1G04GW,125 | SN74HCT1G04DCKR |
|---|---|---|---|---|
| Brand | Nexperia | Nexperia | Nexperia | Texas Instruments |
| Package | 5-TSSOP (SOT353/UMT5) | 5-TSSOP (SOT353/UMT5) - same | 5-TSSOP (SOT353/UMT5) - same | 5-TSSOP (SC70-5 pin-compatible) |
| Logic Family | HCT (TTL input) | HCT (TTL input) | HC (CMOS input) | HCT (TTL input) |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 2.0 V to 6.0 V | 4.5 V to 5.5 V |
| Propagation Delay (typ) | 27 ns | 27 ns | ~25 ns | ~30 ns |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C |
| Automotive Qualified | No | Yes (AEC-Q100) | No | No |
| RoHS / Lead-Free | Yes | Yes | Yes | Yes |
| Approx. Unit Price (qty 1) | $0.42 | $0.95 | $0.38 | $0.45 |
主要差異化特點
- Automotive-grade variant available in identical footprint (對比74HCT1G04GW-Q100H)
- TTL-compatible input thresholds (對比74HC1G04GW,125)
- Standardized TSSOP-5 pinout across vendors (對比SN74HCT1G04DCKR)
設計說明
Decouple VCC (pin 5) with a 0.1 uF X7R ceramic capacitor placed within 3 mm of the pin. The 74HCT1G04GW draws negligible quiescent current at DC, but fast output edges inject brief VCC currents that must be supplied locally. A bulk 1 uF capacitor on the VCC rail near groups of single-gate devices further reduces supply droop during simultaneous switching.
If the input can exceed VCC (for example during hot-plug or fault conditions), add an external current-limiting resistor in series with the input. The on-chip clamp diodes conduct at roughly 1 mA and must not be exceeded; limiting the input current to < 20 mA keeps the diode within its SOA per the Nexperia datasheet. Failure to limit input current can cause latch-up or permanent damage.
Keep input and output traces short, especially when the inverter is used to condition a clock or reset line. The TSSOP-5 footprint leaves pin 1 (NC) free; use that pad as a guard trace to GND if the surrounding routing is dense. Maintain a continuous ground plane beneath the device to keep the GND pin (pin 3) inductance low and the output transition clean.
合規資訊
Standard 74HCT1G04GW is not AEC-Q100; the -Q100H variant carries automotive qualification. RoHS/REACH compliance per Nexperia product page.
