AD9237BCPZRL7-20 - 12-Bit 20 MSPS 3V Low Power ADC | Analog Devices
MPN： AD9237BCPZRL7-20 ✓ 啟用中AD9237BCPZRL7-20 概覽
An ADC is a data converter that transforms continuous analog input signals into discrete digital codes for downstream processing by DSPs, FPGAs, or microcontrollers. The AD9237 family sits at the interface between the analog front-end (amplifiers, filters, sensors) and the digital signal-processing chain, and belongs to the broader category of Nyquist-rate, switched-capacitor, pipeline ADCs. The pipeline architecture uses multiple low-resolution flash stages with inter-stage residue gain and digital error correction, achieving both high sample rate and low latency while consuming milliwatts of power.
Key features include a differential analog input stage with selectable input spans from 1 V p-p to 4 V p-p, an on-chip high-performance sample-and-hold amplifier (SHA), an internal 1.0 V voltage reference, and a CMOS-compatible output stage with an Output Enable pin for bus multiplexing. The ADC consumes only 65 mW typical at 20 MSPS with AVDD = 3 V, making it one of the lowest-power 12-bit ADCs of its speed class. The pin-compatible AD9235 (12-bit, 20/40/65 MSPS) further simplifies system migration paths and reduces design complexity across product generations.
The AD9237 uses a differential switched-capacitor pipeline core with proprietary SHA architecture that minimizes distortion at the front-end and supports a wide common-mode input range, allowing direct DC-coupling from differential drivers such as the AD8138 or AD8352. The on-chip bandgap reference and reference buffer maintain low temperature drift, and the Output Enable pin allows multiple ADCs to share a digital bus, simplifying board routing in multi-channel systems.
Typical applications include portable and battery-powered imaging systems, medical ultrasound front-ends, low-cost I/Q baseband digitizers, hand-held oscilloscope input channels, and industrial inspection cameras. The wide input range scaling also makes it suitable for IF sampling in software-defined radio receivers.
When designing with the AD9237BCPZRL7-20, ensure the analog and digital grounds are star-connected to the exposed pad thermal/epitaxy paddle, which must be soldered to a low-impedance ground plane for electrical performance and thermal dissipation. Use a differential input drive topology with a balun or fully differential amplifier for optimum SFDR, and decouple AVDD and DRVDD with 0.1 uF and 10 uF ceramic capacitors placed within a few millimeters of each supply pin.
直接替換替代品，適用於 AD9237BCPZRL7-20 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： AD9237BCPZRL7-20 （相同外形與佔位） — 差異在於 Architecture, Package, Analog Input Type, Analog Supply Voltage (AVDD), DNL.
AD9235BCPZRL7-20
✅ 直接替換📋 參考替代品（不在目錄中）
AD9237BCPZ-40
✅ 直接替換📋 參考替代品（不在目錄中）
AD9237BCPZ-65
✅ 直接替換聯絡詢價
查看資料表 →AD9237BCPZ-20
✅ 直接替換聯絡詢價
查看資料表 →AD9629BCPZRL7-20
✅ 直接替換📋 參考替代品（不在目錄中）
AD9237BCPZRL7-20 最大額定值與電氣特性
| 解析度 | 12 bits |
| Sample Rate (Grade -20) | 20 MSPS |
| Family Maximum Sample Rate | 65 MSPS |
| Architecture | Pipelined, single-channel |
| Number of Inputs | 1 |
| Analog Supply Voltage (AVDD) | 3 V |
| Digital Output Supply (DRVDD) | 2.5 V |
| Differential Input Span | 1 V p-p to 4 V p-p (selectable) |
| DNL (Differential Nonlinearity) | ±0.7 LSB |
| SNR to Nyquist (at 65 MSPS) | 66 dBc |
| SFDR to Nyquist (at 65 MSPS) | 80 dBc |
| Power Consumption at 20 MSPS | 65 mW typical |
| Input Type | Differential |
| Reference | Internal 1.0 V (external optional) |
| Output Enable Pin | Yes (for bus multiplexing) |
| 封裝 | 32-LFCSP-WQ (5 mm x 5 mm) with exposed pad |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
AD9237BCPZRL7-20 腳位配置
| 腳位 1 | AVDD — Analog supply voltage (3 V) |
| 腳位 2 | AIN+ — Differential analog input positive |
| 腳位 3 | AIN- — Differential analog input negative |
| 腳位 4 | VREF — Voltage reference input/output (1.0 V internal) |
| 腳位 5 | AGND — Analog ground |
| 腳位 6 | SENSE — Reference mode select (internal/external) |
| 腳位 7 | DRVDD — Digital output driver supply (2.5 V) |
| 腳位 8 | DRGND — Digital ground |
| 腳位 9 | D0 — Data output bit 0 (LSB) |
| 腳位 10 | D1 — Data output bit 1 |
| 腳位 11 | D2 — Data output bit 2 |
| 腳位 12 | D3 — Data output bit 3 |
| 腳位 13 | D4 — Data output bit 4 |
| 腳位 14 | D5 — Data output bit 5 |
| 腳位 15 | D6 — Data output bit 6 |
| 腳位 16 | D7 — Data output bit 7 |
| 腳位 17 | D8 — Data output bit 8 |
| 腳位 18 | D9 — Data output bit 9 |
| 腳位 19 | D10 — Data output bit 10 |
| 腳位 20 | D11 — Data output bit 11 (MSB) |
| 腳位 21 | OTR — Out-of-range indicator |
| 腳位 22 | DRVDD — Digital output driver supply (2.5 V) |
| 腳位 23 | CLK+ — Clock input positive |
| 腳位 24 | CLK- — Clock input negative (complementary) |
| 腳位 25 | AGND — Analog ground |
| 腳位 26 | AVDD — Analog supply voltage (3 V) |
| 腳位 27 | PDWN — Power-down control (active high) |
| 腳位 28 | OE — Output enable (active high, for bus multiplexing) |
| 腳位 29 | AGND — Analog ground |
| 腳位 30 | AVDD — Analog supply voltage (3 V) |
| 腳位 31 | DRGND — Digital ground |
| 腳位 32 | EP — Exposed pad (connect to AGND/DRGND) |
典型應用
AD9237BCPZRL7-20 適用於 6 應用s: Portable Medical Ultrasound Imaging, Industrial Inspection Cameras and Machine Vision, Handheld Oscilloscope Input Channels, IF Sampling in Software-Defined Radio Receivers, Battery-Powered Data Acquisition Systems, Low-Cost Multi-Channel Ultrasound Beamformer.
Portable Medical Ultrasound Imaging
The AD9237BCPZRL7-20's 12-bit resolution, 20 MSPS sample rate, and 65 mW typical power consumption make it well-suited for handheld and portable ultrasound imaging front-ends where per-channel power budget is critical. Multi-channel arrays parallel multiple AD9237 devices with the Output Enable pin simplifying bus multiplexing; the selectable 1-4 V p-p differential input range accommodates the variable output levels from ultrasound preamplifiers without external attenuators. Unlike higher-speed ADCs, the -20 grade keeps thermal load low across 32+ channel probe heads, extending battery runtime in cart-based systems.
推薦
Industrial Inspection Cameras and Machine Vision
The AD9237BCPZRL7-20 provides the 12-bit dynamic range and 20 MSPS throughput needed to digitize CCD/CIS sensor outputs in line-scan and area-scan industrial inspection cameras. The 66 dBc SNR to Nyquist preserves subtle intensity gradients critical for defect detection, while the LFCSP-32 (5x5 mm) footprint fits compact camera head enclosures. The differential input stage rejects common-mode noise from factory floor environments, and the Output Enable pin allows pixel-synchronous bus arbitration when multiple ADCs share a controller bus.
推薦
Handheld Oscilloscope Input Channels
Battery-powered handheld oscilloscopes benefit from the AD9237BCPZRL7-20's 65 mW power dissipation and 20 MSPS sample rate, which extends battery life while delivering 12-bit vertical resolution for low-amplitude waveform capture. The selectable 1-4 V p-p input range allows direct coupling from front-end attenuators without intermediate gain stages, simplifying BOM and reducing calibration complexity. The LFCSP-32 package with exposed pad provides low thermal resistance for sustained acquisition bursts in compact handheld form factors.
推薦
IF Sampling in Software-Defined Radio Receivers
The AD9237BCPZRL7-20's 12-bit resolution and 20 MSPS sample rate make it suitable for low-IF sampling in narrowband SDR receivers, including Ham radio, public-safety, and shortwave applications. The 80 dBc SFDR preserves spurious-free dynamic range needed for weak-signal demodulation, and the differential input stage rejects common-mode LO leakage. Its lower sample rate (vs the -65 grade) reduces power consumption, which is critical for portable SDR designs where battery life and heat dissipation dominate design trade-offs.
推薦
Battery-Powered Data Acquisition Systems
Portable field data acquisition systems (DAQ) in environmental monitoring, structural health, and remote telemetry leverage the AD9237BCPZRL7-20's 65 mW typical power consumption and 20 MSPS sample rate to digitize sensor signals while extending battery life over multi-day field deployments. The 12-bit resolution is sufficient for vibration, strain gauge, and temperature-sensor digitisation, while the LFCSP-32 footprint fits pocket-sized form factors. The Output Enable pin enables bus sharing between multiple ADC instances for synchronized multi-channel acquisition.
推薦
Low-Cost Multi-Channel Ultrasound Beamformer
The AD9237BCPZRL7-20 enables low-cost beamformer front-ends in diagnostic ultrasound by combining its 12-bit vertical resolution with low per-channel power at 20 MSPS. Designers can parallel 16, 32, or 64 AD9237 devices with shared digital buses using the Output Enable pin for time-multiplexed data transfer to a downstream FPGA. The selectable 1-4 V p-p input range accommodates TGC (time-gain-compensated) transducer signals without range switching, and the small 5x5 mm LFCSP package supports dense array layouts.
推薦
推薦產品摘要
工程參考資料，適用於 AD9237BCPZRL7-20 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | AD9235BCPZRL7-20 | AD9237BCPZ-40 | AD9237BCPZ-65 | AD9237BCPZ-20 | AD9629BCPZRL7-20 |
|---|---|---|---|---|---|---|
| Package | 32-LFCSP-WQ (5x5) | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same | 32-LFCSP (5x5) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sample Rate | 20 MSPS | 20 MSPS | 40 MSPS | 65 MSPS | 20 MSPS | 20 MSPS |
| Analog Supply Voltage | 3 V | 3 V | 3 V | 3 V | 3 V | 3 V |
| Power Consumption | 65 mW at 20 MSPS | 65 mW at 20 MSPS | 135 mW at 40 MSPS | 190 mW at 65 MSPS | 65 mW at 20 MSPS | 70 mW at 20 MSPS |
| Differential Input Span | 1 V p-p to 4 V p-p | Fixed (per AD9235 datasheet) | 1 V p-p to 4 V p-p | 1 V p-p to 4 V p-p | 1 V p-p to 4 V p-p | 1 V p-p to 4 V p-p |
| Output Enable Pin | Yes | Yes | Yes | Yes | Yes | Yes |
主要差異化特點
- Lowest power consumption in the AD9237 family at 20 MSPS grade (對比AD9237BCPZ-65)
- Pin-compatible upgrade path for AD9235 designs (對比AD9235BCPZRL7-20)
- Output Enable pin enables bus multiplexing (對比Non-bus-enabled ADCs)
設計說明
The 32-LFCSP-WQ package uses an exposed thermal pad (EP, pin 32) that MUST be soldered to a low-impedance analog ground plane on the PCB. Use 0.1 uF and 10 uF ceramic decoupling capacitors placed within 2-3 mm of each AVDD and DRVDD pin pair. Star-connect analog and digital grounds at the EP to prevent digital switching noise from coupling into the analog front-end.
Drive the ADC with a differential amplifier such as AD8138 or AD8352 for optimum SFDR (80 dBc to Nyquist). Use a balun if single-ended-to-differential conversion is acceptable and adequate. Route the CLK+/CLK- differential clock traces as a matched-length, impedance-controlled pair (typically 100 ohm differential) and keep them short to minimize jitter.
Do not exceed the maximum analog input swing beyond 4 V p-p differential, as this will cause saturation and degrade linearity. Always enable the internal reference (SENSE pin tied to AGND) or apply a clean external reference to VREF - floating SENSE will cause unstable reference voltage. The Output Enable (OE) pin must be driven high for normal operation; leaving it floating may cause unpredictable output behavior.
合規資訊
RoHS compliant per Analog Devices product page. Not AEC-Q100 qualified - this is a commercial/industrial grade ADC. Halogen-free status not explicitly confirmed in available data.
