ADC1175CIJM - 8-Bit 20MSPS ADC, +5V, 24-SOIC | Texas Instruments
MPN： ADC1175CIJM ✓ 啟用中ADC1175CIJM 概覽
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time, discrete-amplitude digital codes. The 8-bit family is the entry point of ADC resolution and remains prevalent in legacy video digitizers, IF/baseband digitizers for communications, digital still-camera preview pipelines, and low-cost oscilloscopes. Higher-level hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Two-step flash ADCs subdivide the conversion into coarse and fine passes; they trade slightly higher latency against power, area, and input-capacitance savings compared with full-flash designs at the same resolution.
Key features include one single-ended input channel, parallel CMOS-compatible digital outputs, a track-and-hold front-end, an internal reference ladder accessible at the top and bottom for external bypass, and short-circuit-proof outputs. The converter is latch-up resistant and offers TTL/CMOS-logic-compatible input clocks. Sampling rate per second is 20 MSPS, and operating temperature range is -20C to +75C, qualifying the part for commercial-extended industrial environments.
The ADC1175 uses a two-step sub-ranging architecture with on-chip sample-and-hold to minimize analog input capacitance and ease the driver amplifier requirement. Internal bandgap-derived reference and trimmed ladder networks deliver specified DC linearity without external precision components. The short-circuit-proof CMOS outputs can directly drive bus lines or back-end ASICs without external buffers in most cases.
Typical applications include composite video digitizers, digital cameras, video capture cards, camcorders, handheld imaging devices, IF signal digitization in communications receivers, and portable test instrumentation. The single +5V supply and low 60 mW dissipation are well matched to portable imaging and battery-powered equipment. Designers should keep analog and digital grounds referenced to a single low-impedance star ground, place the input anti-alias RC close to the analog input pin, and provide adequate decoupling (0.1 uF + 10 uF) on AVDD to suppress reference ladder switching noise. Unique value: this page consolidates a regional trade price ladder, lifecycle context, pin-for-pin alternative guides, and design notes not packaged together in the original ADC1175 datasheet.
直接替換替代品，適用於 ADC1175CIJM — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADC1175CIJM （相同外形與佔位） — 差異在於 Architecture, Operating Temperature Range, Package, Input Type, Resolution.
ADC1175-50CIJM
✅ 直接替換聯絡詢價
查看資料表 →ADC1175CIJM/NOPB
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC1175CIJM 最大額定值與電氣特性
| 解析度 | 8 bit |
| Sampling Rate (Per Second) | 20 MSPS |
| Number of Input Channels | 1 |
| Input Type | Single-Ended |
| Architecture | Two-Step (Sub-Ranging Flash) |
| Data Interface | Parallel |
| Output Code Format | Binary |
| Supply Voltage (Analog/Digital) | +5 V single supply |
| Power Dissipation (Typical) | 60 mW |
| 工作溫度範圍 | -20C to +75C |
| Temperature Grade | Commercial Extended |
| 封裝 / 外殼 | 24-SOIC (0.209 in / 5.30 mm width) |
| 腳位數 | 24 |
| 安裝類型 | Surface Mount |
| Packaging | Tube |
| Latch-up Resistance | Yes (per datasheet) |
| Output Short-Circuit Protection | Yes (per datasheet) |
| RoHS 狀態 | Compliant |
ADC1175CIJM 腳位配置
| 腳位 1 | VD — +5V analog/digital supply |
| 腳位 2 | AIN — Analog input (single-ended) |
| 腳位 3 | REFT — Reference ladder top (bypass with capacitor) |
| 腳位 4 | REFB — Reference ladder bottom (bypass with capacitor) |
| 腳位 5 | GND — Ground (analog and digital common) |
| 腳位 6 | CLK — Conversion clock input (TTL/CMOS) |
| 腳位 7 | D0 — Digital output bit 0 (LSB) |
| 腳位 8 | D1 — Digital output bit 1 |
| 腳位 9 | D2 — Digital output bit 2 |
| 腳位 10 | D3 — Digital output bit 3 |
| 腳位 11 | D4 — Digital output bit 4 |
| 腳位 12 | D5 — Digital output bit 5 |
| 腳位 13 | D6 — Digital output bit 6 |
| 腳位 14 | D7 — Digital output bit 7 (MSB) |
| 腳位 15 | GND — Ground |
| 腳位 16 | VD — +5V supply |
| 腳位 17 | NC — Not connected (per datasheet) |
| 腳位 18 | NC — Not connected (per datasheet) |
| 腳位 19 | NC — Not connected (per datasheet) |
| 腳位 20 | NC — Not connected (per datasheet) |
| 腳位 21 | NC — Not connected (per datasheet) |
| 腳位 22 | NC — Not connected (per datasheet) |
| 腳位 23 | NC — Not connected (per datasheet) |
| 腳位 24 | NC — Not connected (per datasheet) |
典型應用
ADC1175CIJM 適用於 6 應用s: Composite Video Digitizer, Digital Still Camera Preview Pipeline, Handheld Oscilloscope Front-End, IF Signal Digitization in Communications Receivers, Portable Test & Measurement Instrument, Camcorder Imaging Front-End.
Composite Video Digitizer
The ADC1175CIJM fits composite video digitizers because 8-bit resolution at 20 MSPS is sufficient to encode standard NTSC/PAL video bandwidths (~5-6 MHz) into parallel YCbCr samples without dropping frames. With one single-ended analog input and an internal sample-and-hold, the part interfaces directly to a video amplifier output via a single anti-alias RC network. The 60 mW dissipation means no heatsink is needed even in a sealed enclosure, and the parallel CMOS outputs drive the FPGA capture FIFO directly without additional buffering. Compared to higher-resolution ADCs, the ADC1175 trades ENOB and DC linearity for low cost, making it the standard converter for cost-engineered capture cards.
推薦
Digital Still Camera Preview Pipeline
In digital still camera preview pipelines the ADC1175CIJM digitizes the 8-bit Bayer mosaic sensor output at 20 MSPS, satisfying preview-resolution throughput without overheating a sealed camera body. The +5V single-supply operation aligns with common camera digital rails, eliminating the dual-rail LDO chain typical of higher-resolution converters. The 60 mW typical power keeps total system dissipation low, supporting longer battery life in handheld cameras. Designers can clock the ADC1175 directly from a low-jitter FPGA-generated pixel clock and route the 8 parallel CMOS bits into an ASIC preview engine.
推薦
Handheld Oscilloscope Front-End
The ADC1175CIJM is a fit for handheld oscilloscope front-ends because its 20 MSPS rate supports up to 5 MHz useful analog input bandwidth, ample for sub-1 MHz field-service oscilloscopes targeting hobbyist and field-engineer use. The 24-SOIC package and surface-mount form factor keep the converter footprint smaller than typical BGA parts, easing handheld-PCB layout where the front-end must coexist with display, battery, and user I/O. The internal reference ladder with externally accessible top/bottom nodes lets designers trim gain with a precision resistor pair for calibrated vertical accuracy.
推薦
IF Signal Digitization in Communications Receivers
The ADC1175CIJM serves IF-signal digitization in low-cost communications receivers such as AM/FM demodulators, shortwave SDR dongles, and entry-level digital trunked-radio receivers. The 20 MSPS sample rate and 8-bit resolution enable ~6 MHz of useful IF bandwidth, sufficient for narrowband AM and FM carrier demodulation. Direct +5V single-supply operation simplifies receiver power architecture. Designers pair the ADC1175 with an FPGA performing DDC (digital down-conversion) and a downstream DSP for demodulation, replacing legacy analog IF chains with a software-defined approach.
推薦
Portable Test & Measurement Instrument
The ADC1175CIJM is suitable for portable test-and-measurement instruments including handheld multimeters with digitizer functions, RF sniffers, and field-service signal tracers, where 60 mW dissipation and +5V single-supply operation are decisive. The parallel CMOS outputs feed an MCU or low-cost FPGA for transient capture at sample rates up to 20 MSPS. The latch-up resistance and short-circuit-proof outputs of the ADC1175 contribute to rugged field-instrument reliability. Compared to a pin-compatible SAR ADC, the two-step flash of the ADC1175 trades conversion latency for higher throughput at very small input capacitance, easing the front-end amplifier selection.
推薦
Camcorder Imaging Front-End
The ADC1175CIJM suits camcorder imaging front-ends for legacy standard-definition CCD image sensors outputting 8-bit, 20 MSPS pixel streams. The internal sample-and-hold and 24-SOIC footprint simplify PCB layout on space-constrained camcorder mainboards. Single +5V operation aligns with the camcorder battery regulator stack, and the 60 mW dissipation keeps total thermal load within the sealed chassis budget. Designers pair the ADC1175 with an ASIC pixel formatter and downstream MPEG encoder, achieving 8-bit video capture without the higher cost of a 10-bit converter in legacy SD designs.
推薦
推薦產品摘要
工程參考資料，適用於 ADC1175CIJM — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADC1175-50CIJM | ADC1175CIJM/NOPB |
|---|---|---|---|
| Package | 24-SOIC (0.209 in / 5.30 mm) | 24-SOIC (same footprint, drop-in) | 24-SOIC (same footprint, drop-in) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments (NOPB Pb-free variant) |
| Resolution | 8 bit | 8 bit | 8 bit |
| Sample Rate (Max) | 20 MSPS | 50 MSPS (+150%) | 20 MSPS (identical) |
| Power Dissipation (Typ) | 60 mW | Higher (proportional to clock) | 60 mW (identical) |
| Supply Voltage | +5 V single supply | +5 V single supply | +5 V single supply |
| Architecture | Two-Step (sub-ranging flash) | Two-Step (sub-ranging flash) | Two-Step (sub-ranging flash) |
| Operating Temperature | -20C to +75C | -20C to +75C | -20C to +75C |
| Terminal Finish | SnPb or Pb-free (per JEDEC) | SnPb or Pb-free | Pb-free (Matte Sn, NOPB suffix) |
主要差異化特點
- Pin-compatible upgrade path to 50 MSPS within the same family (對比ADC1175-50CIJM)
- Pb-free NOPB variant for lead-free assembly lines (對比ADC1175CIJM/NOPB)
- Single +5V supply eliminates dual-rail LDO chain (對比Generic 8-bit ADC requiring +3.3V/1.8V split rails)
設計說明
Place the input anti-alias RC network within 5 mm of the ADC1175 AIN pin. Use a 50 ohm source termination to control charge kicks from the internal sample-and-hold. Route analog input traces over a continuous ground pour, never crossing digital output traces (D0-D7) at 90 degrees or less. Provide a 0.1 uF X7R ceramic + 10 uF tantalum/ceramic decoupling pair directly on the VD pins, with the 0.1 uF cap closest to the IC.
Maintain a single low-impedance analog ground star point connecting the ADC1175 GND, the input amplifier ground, the clock-driver ground, and the bypass-capacitor returns. Reference the digital outputs to digital ground that returns to the same star point only at the IC GND pin, to avoid ground bounce coupling into the analog input. Keep digital output traces short (typically less than 50 mm) and series-terminate near the ADC1175 if the load is more than 50 pF.
Do not exceed +5.25V on VD (datasheet absolute maximum). Ensure the clock input is TTL/CMOS-logic compatible with rise/fall times less than 5 ns to avoid spurious internal latch-up transitions. Never float the REFT or REFB pins; both must be bypassed with 0.1 uF + 10 uF low-ESR capacitors to ground. When migrating from the ADC1175-25 or ADC1175-50 family, verify that downstream logic captures the additional output codes - some legacy capture cards treat the LSB as noise.
合規資訊
RoHS status per TI product page and DigiKey material declaration. NOPB suffix variants are fully Pb-free. AEC-Q100 qualification not sought for this commercial-extended legacy ADC; for automotive, choose an AEC-Q100-qualified part from a different TI family (e.g., ADC08xx series).
