ADS4226IRGC25 - 12-Bit 160MSPS Dual-Channel ADC | Texas Instruments
MPN： ADS4226IRGC25 ✓ 啟用中ADS4226IRGC25 概覽
An ADC (analog-to-digital converter) is a mixed-signal data converter that translates continuous-time analog input signals into discrete digital codes at a sampling rate governed by an external clock. In the system hierarchy, ADCs sit at the boundary between the analog front end (amplifiers, filters, sensors) and the digital signal processor or FPGA that consumes the resulting data words. The ADS4226 belongs to the high-speed pipelined ADC class, which sacrifices absolute latency for throughput and is preferred when wideband IF/RF signals, radar returns, or high-speed imaging must be digitized in real time.
Key features of the ADS4226 include 12-bit resolution with no missing codes, a 160 MSPS maximum sample rate, 70.4 dBFS SNR at 70 MHz input and 78 dBc SFDR, LVDS-compatible DDR output interface, and integrated input buffer and reference. The device accepts differential analog inputs centered on a 1.5 V common-mode and offers LVDS/CMOS interface options. Its pipeline architecture enables concurrent two-channel operation with channel-to-channel gain and offset matching suitable for diversity receivers.
Typical applications for the ADS4226 include wireless communications basestation receivers, radar and lidar digitizers, medical imaging front ends, high-speed oscilloscopes, and software-defined radio platforms. The wide input bandwidth (~600 MHz -3 dB) and high SFDR make it well suited to undersampling IF signals in multicarrier GSM/WCDMA/LTE receivers and to digitizing the wideband IFs found in test and measurement instrumentation.
When designing with the ADS4226IRGC25, decouple AVDD/DVDD with 1 uF and 0.1 uF ceramic capacitors placed within 2 mm of each supply pin, keep the analog input traces length-matched and 100 ohm differential, and use the integrated DC-coupling path to simplify the front-end filter. A matched impedance, length-balanced layout to the FPGA/ASIC is essential to preserve the LVDS DDR timing budget.
This page synthesizes distributor pricing as of 2026-10-12, drop-in same-package alternatives, application-specific design notes, and a parameter comparison table that complements the TI datasheet.
直接替換替代品，適用於 ADS4226IRGC25 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS4226IRGC25 （相同外形與佔位） — 差異在於 Package, Number of Channels, Output Interface, Architecture, Input Type.
ADS4226IRGCT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS4225IRGC25
✅ 直接替換📋 參考替代品（不在目錄中）
ADS4222IRGC25
✅ 直接替換📋 參考替代品（不在目錄中）
ADS62P23IRGC25
✅ 直接替換聯絡詢價
查看資料表 →ADS62P22IRGC25
✅ 直接替換聯絡詢價
查看資料表 →ADS6242IRGZR
✅ 直接替換聯絡詢價
查看資料表 →ADS4226IRGC25 最大額定值與電氣特性
| 解析度 | 12 bit |
| Number of Channels | 2 (dual) |
| Sample Rate (max) | 160 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Analog Supply Voltage | 1.8 V (1.7 V to 1.9 V) |
| Digital Supply Voltage | 1.8 V (1.7 V to 1.9 V) |
| Power Dissipation | 198 mW per channel at 160 MSPS |
| SNR | 70.4 dBFS at 70 MHz Fin, 160 MSPS |
| SFDR | 78 dBc at 70 MHz Fin |
| Input Bandwidth (-3 dB) | ~600 MHz |
| Output Interface | LVDS DDR (or parallel CMOS) |
| 封裝 | 64-pin VQFN (RGC) 9x9 mm with exposed pad |
| 工作溫度 | -40C to +85C (industrial) |
| RoHS 狀態 | Compliant |
| Integrated Input Buffer | Yes |
| On-chip Reference | Internal |
ADS4226IRGC25 64-pin vqfn (rgc) 9x9 mm with exposed pad 腳位配置指南
ADS4226IRGC25（64-pin vqfn (rgc) 9x9 mm with exposed pad 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： ADS4226IRGC25.
請參閱 資料表 以查看完整腳位配置。
典型應用
ADS4226IRGC25 適用於 6 應用s: Wireless Basestation Receiver, Radar and Lidar Digitizer, Medical Imaging Front End, High-Speed Oscilloscope and Test Equipment, Software-Defined Radio Platform, Industrial Non-Destructive Testing.
Wireless Basestation Receiver
The ADS4226IRGC25 is a strong fit for multicarrier GSM, WCDMA and LTE basestation IF digitizers, where two diversity channels must be sampled simultaneously at high SFDR. With 70.4 dBFS SNR, 78 dBc SFDR, and 600 MHz input bandwidth, the device can undersample IF frequencies up to 200 MHz while preserving the dynamic range required for 3GPP adjacent-channel leakage ratio and noise-figure budgets. The 1.8 V supply and 198 mW per channel power keep thermal load manageable in dense line cards.
推薦
Radar and Lidar Digitizer
Wide input bandwidth and 12-bit resolution at 160 MSPS make the ADS4226IRGC25 well suited to digitizing the intermediate frequency output of FMCW and pulsed radar receivers, as well as time-of-flight lidar front ends. The dual channels allow simultaneous capture of the in-phase and quadrature IF signals, while the LVDS DDR output minimizes FPGA pin usage. SFDR above 78 dBc prevents spurious responses from masking weak targets, critical for long-range detection.
推薦
Medical Imaging Front End
The ADS4226IRGC25 can be paired with a low-noise transimpedance amplifier to digitize ultrasound, PET, or optical coherence tomography detector outputs. Its dual channels allow simultaneous A-scan capture from two transducer elements, while the integrated input buffer reduces the analog front-end complexity. The 1.8 V supply and 198 mW per channel help meet IEC 60601 thermal and patient-safety constraints, and the 12-bit resolution is sufficient for many B-mode ultrasound applications.
推薦
High-Speed Oscilloscope and Test Equipment
Bench oscilloscopes, spectrum analyzers, and wideband digitizers benefit from the ADS4226IRGC25's 160 MSPS sample rate and 600 MHz input bandwidth. Two matched channels per device simplify interleaved designs and reduce calibration overhead. The integrated input buffer eliminates the need for an external ADC driver, and the LVDS DDR interface streams data directly to an FPGA for real-time FFT and trigger processing. SFDR of 78 dBc preserves measurement integrity in production test stations.
推薦
Software-Defined Radio Platform
Software-defined radio receivers covering HF, VHF and UHF bands can use the ADS4226IRGC25 as a direct-IF sampler. The 600 MHz analog input bandwidth supports direct sampling of low-IF and zero-IF architectures, and the dual channels permit I/Q capture from a single chip. The on-chip input buffer simplifies interface to RF transformers, and the LVDS DDR output feeds directly into DSP FPGA fabrics for channelization and demodulation.
推薦
Industrial Non-Destructive Testing
Phased-array ultrasonic and eddy-current inspection systems can use the ADS4226IRGC25 to digitize multiple receive channels in parallel. The 12-bit resolution and 160 MSPS rate are adequate for capturing echo signatures from defects, while the dual channels allow dense channel packing on the inspection probe. Industrial-grade -40C to +85C operation supports deployment in factory and field environments, and the low 198 mW per channel power reduces cooling requirements in sealed housings.
推薦
推薦產品摘要
工程參考資料，適用於 ADS4226IRGC25 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS4226IRGCT | ADS4225IRGC25 | ADS4222IRGC25 | ADS62P23IRGC25 | ADS62P22IRGC25 | ADS6242IRGZR |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit |
| Max Sample Rate | 160 MSPS | 160 MSPS | 125 MSPS | 65 MSPS | 80 MSPS | 65 MSPS | 65 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| Output Interface | LVDS DDR | LVDS DDR | LVDS DDR | LVDS DDR | LVDS | LVDS | LVDS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Ultralow power at 160 MSPS per channel (對比ADS62P23IRGC25)
- Pin-compatible speed grades inside TI family (對比ADS4225IRGC25)
- Dual-channel at 160 MSPS in a single chip (對比ADS6242IRGZR)
設計說明
The ADS4226IRGC25 requires a clean 1.8 V analog and 1.8 V digital supply. Place a 1 uF X7R ceramic plus a 0.1 uF X7R ceramic within 2 mm of each AVDD pin and route AVDD/DVDD through a ferrite bead to suppress digital switching noise on the analog rail. Estimated: total supply current at 160 MSPS is approximately 220 mA, so budget at least 0.5 A on the AVDD LDO to avoid dropout at cold temperature.
Route the differential analog inputs (AINP/AINM) as a 100 ohm differential pair with length matching within 0.5 mm. The LVDS data and clock pairs must be length matched within 0.25 mm and routed over a continuous ground reference plane to maintain 100 ohm differential impedance. The exposed pad (EP) of the VQFN-64 must be soldered to a continuous ground pad with 9 to 13 thermal vias for heat dissipation.
Do not float the SDATA and SCLK pins; if serial programming is not used, tie SCLK to ground and leave SDATA open. The LVDS termination resistors (100 ohm) must be placed at the receiver end, not at the ADC outputs. Avoid routing analog inputs parallel to digital LVDS pairs to prevent digital-to-analog coupling, and use the integrated input buffer rather than a passive input network to preserve the bandwidth above 500 MHz.
The LVDS DDR interface toggles at 320 Mbps per channel; use a 100 ohm differential termination at the FPGA receiver and add a small AC-coupling capacitor if DC balance is a concern. The clock-to-data skew at the FPGA must be calibrated to within 100 ps to meet the LVDS DDR setup/hold time, which usually requires per-board training. Power supply decoupling for the AVDD/DVDD pins is critical: use 0402-sized ceramics placed symmetrically around the package perimeter.
合規資訊
RoHS and lead-free per TI ADS4226 product page. Not AEC-Q100 qualified; the ADS4226 is positioned for industrial/consumer basestation and test equipment. Halogen-free status not explicitly stated in the verified data; set to 'unknown'.
