CD4060BE - 14-Bit CMOS Counter | Texas Instruments
MPN： CD4060BE ✓ 啟用中CD4060BE 概覽
A CMOS binary counter is a sequential digital-logic device that advances an internal state when triggered by a clock edge. A ripple-carry counter connects multiple flip-flop stages so each output changes at a divided frequency derived from the preceding stage. The CD4060BE combines that counting function with an oscillator, allowing one package to generate a timing reference and divide it into multiple frequency outputs without requiring a separate clock source.
The CD4060BE's key features include 14 counter stages, a maximum clock frequency of 24 MHz, operation across a 3 V to 18 V supply range, and a 16-pin plastic DIP package. Its oscillator can be configured for either RC timing or crystal timing. A master-reset input establishes the all-zero counter state, making the device useful when a defined startup state or synchronized clearing action is required.
Internally, the counter is implemented as a chain of ripple-carry binary stages. Each output provides one binary bit of the accumulated count, while the stage spacing creates successively divided clock signals. The oscillator section supplies a convenient internal timing source for designs that do not need an external clock generator. Because this is CMOS logic, the supply voltage range supports both lower-voltage and higher-voltage system designs within the device's specified limits.
Typical applications include binary event counters, frequency dividers, periodic-pulse generators, digital time bases, oscillator modules, clock-generation circuits, and industrial control or instrumentation systems. The oscillator-and-divider combination is especially useful when a system requires several related frequency outputs generated from one timing network.
When constructing the circuit, keep oscillator components close to the OSC_IN and OSC_OUT pins, provide a clean and stable supply, and use a reset strategy that prevents invalid counter states during power-up. Crystal timing generally requires carefully selected load and stability components, while RC timing trades frequency precision for component simplicity. The 16-pin DIP package also requires adequate spacing around the device for socketed or hand-soldered assembly.
This product page combines the manufacturer device description, distributor identification, cross-reference candidates, and application-oriented engineering guidance. It also distinguishes genuine 16-pin through-hole drop-in options from devices that use different package formats, helping designers shorten replacement work without overlooking pinout, voltage, or timing differences.
直接替換替代品，適用於 CD4060BE — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
HEF4060BP,652
✅ 直接替換📋 參考替代品（不在目錄中）
CD4060BCN
✅ 直接替換📋 參考替代品（不在目錄中）
CD4060BE 最大額定值與電氣特性
| Product Type | 14-stage ripple-carry binary counter, divider, and oscillator |
| Logic Family | CMOS |
| Number of Counter Stages | 14 stages |
| Number of Binary Outputs | 14 outputs |
| 最大時脈頻率 | 24 MHz |
| Supply Voltage Range | 3 V to 18 V |
| Clock Edge Sensitivity | Negative edge |
| Oscillator Timing Modes | RC or crystal oscillator |
| Master Reset Function | Resets counter outputs to all 0 |
| Counter Technology | Ripple-carry binary counter |
| Package Type | 16-pin plastic DIP |
| Package Pin Count | 16 pins |
| 安裝類型 | Through-hole |
CD4060BE 腳位配置
| 腳位 1 | OSC_OUT — Oscillator output |
| 腳位 2 | OSC_IN — Oscillator input |
| 腳位 3 | MR — Master reset input |
| 腳位 4 | Q0 — Counter output 0 |
| 腳位 5 | Q1 — Counter output 1 |
| 腳位 6 | Q2 — Counter output 2 |
| 腳位 7 | Q3 — Counter output 3 |
| 腳位 8 | VSS — Ground reference |
| 腳位 9 | Q4 — Counter output 4 |
| 腳位 10 | Q5 — Counter output 5 |
| 腳位 11 | Q6 — Counter output 6 |
| 腳位 12 | Q7 — Counter output 7 |
| 腳位 13 | Q8 — Counter output 8 |
| 腳位 14 | Q9 — Counter output 9 |
| 腳位 15 | Q10 — Counter output 10 |
| 腳位 16 | VDD — Positive power supply |
典型應用
CD4060BE 適用於 6 應用s: Binary Event Counter, Frequency Divider, RC Oscillator Module, Periodic Pulse Generator, Digital Time Base, Industrial Control Retiming.
Binary Event Counter
The CD4060BE suits designs that must count recurring input events and expose the result across 14 binary outputs. Each of the 14 ripple-carry stages represents a separate binary count position, allowing the same circuit to monitor low-order event counts and longer-term totals. With a documented maximum clock frequency of 24 MHz, it can process fast pulse trains when timing margins are adequate. The 3 V to 18 V supply range also supports both compact low-voltage logic and higher-voltage legacy systems. Use a negative-edge input signal, establish a defined reset state, and account for propagation delay when sampling the binary outputs.
推薦
Frequency Divider
The CD4060BE can divide a clock into several related binary-rate outputs without requiring fourteen separate divider circuits. Its 14 ripple-carry stages provide progressively divided signals, and the maximum clock frequency of 24 MHz gives designers headroom for moderate-rate digital systems. The oscillator section may generate the source clock directly, or an external clock can be applied at the timing input. Because the outputs are generated through a ripple chain, downstream timing should include the cumulative propagation delay of the stages being used. A 16-pin DIP package also makes the device convenient for prototypes and through-hole industrial assemblies.
推薦
RC Oscillator Module
The CD4060BE integrates an oscillator with a binary counter, making it suitable for compact periodic-pulse and general timing modules. The oscillator configuration supports RC or crystal timing, giving designers a choice between a simple resistor-capacitor network and a more stable frequency reference. Its 14 counter stages allow the oscillator frequency to be divided into useful lower-rate signals. The 3 V to 18 V operating range supports several logic environments, while the 16-pin plastic DIP package simplifies prototyping and socket-based assembly. Component tolerance, supply variation, and temperature will influence RC timing accuracy, so use crystal timing when frequency stability is more important than simplicity.
推薦
Periodic Pulse Generator
A CD4060BE oscillator followed by selected divider outputs can produce a repeating digital pulse train for control, sequencing, or sampling systems. The 14-stage architecture provides multiple division choices, allowing the same oscillator network to support several timing domains. Its 24 MHz maximum clock frequency supports high-rate timing sources, although the final output rate and load must remain compatible with the selected stage. The master reset offers a way to initialize the counter to its all-zero state. For a stable interval reference, verify oscillator startup and frequency tolerance over the intended temperature and supply range before using the generated pulses as a precision time base.
推薦
Digital Time Base
The CD4060BE can form the core of a simple digital time-base circuit by combining its internal oscillator with the 14 available divided outputs. A crystal timing configuration can provide a more stable reference than an RC network, while outputs at different division ratios can drive seconds, milliseconds, or other system intervals after appropriate scaling. The counter is implemented in CMOS and operates from 3 V to 18 V, permitting use across legacy and modern logic voltage domains. Timing accuracy depends on the oscillator network, supply stability, and selected output stage. The 16-pin DIP format is especially practical where a socketed module or hand-assembled instrument is planned.
推薦
Industrial Control Retiming
The CD4060BE is useful for industrial control circuits that need to pace events, divide a system clock, or create delayed and periodic control pulses. Its 14-stage ripple-carry counter provides multiple timing taps, while the 3 V to 18 V supply range allows integration with different logic voltage domains. The master-reset input supports deterministic initialization during startup or a controlled subsystem restart. Because ripple stages propagate sequentially, firmware or discrete logic should sample outputs with sufficient settling time and should avoid treating simultaneous transitions as perfectly aligned. The 16-pin DIP package provides generous physical spacing for panel wiring and serviceable through-hole assembly.
推薦
推薦產品摘要
工程參考資料，適用於 CD4060BE — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | HEF4060BP,652 | CD4060BCN |
|---|---|---|---|
| Package | 16-pin plastic DIP | 16-pin DIP - same package format | 16-pin DIP - same package format |
| Brand | Texas Instruments | NXP | Fairchild |
| Counter Stages | 14 stages | 14-stage CD4060-family counter | 14-stage counter |
| Oscillator Support | RC or crystal oscillator | CD4060-family oscillator-counter function | CD4060-family oscillator-counter function |
| Logic Technology | CMOS | CMOS | CMOS |
主要差異化特點
- Broader documented maximum supply voltage (對比CD4060BCN)
- Integrated oscillator and 14-stage divider in one through-hole package (對比HEF4060BP,652)
- Negative-edge counting and deterministic all-zero reset (對比CD4060BCN)
設計說明
Place oscillator timing components and their return paths close to the OSC_IN and OSC_OUT pins. A long loop around the timing network can increase noise pickup or unintended feedback, particularly when an RC oscillator is used. Keep the master-reset trace away from oscillator nodes, provide a ground reference near pin 8, and place input/output decoupling close to the associated supply pins.
Treat ripple-counter outputs as sequential signals rather than simultaneously changing clock edges. When a downstream circuit samples multiple outputs, allow the cumulative propagation delay of the ripple stages to settle before latching the value. At high clock rates, confirm that the selected output frequency, load, and timing margin remain within the device's documented operating conditions.
Do not substitute an SOIC or other surface-mount package for the CD4060BE without redesigning the PCB footprint; a true physical replacement must use the same 16-pin DIP format and pinout. Also verify oscillator component values, reset polarity, and supply voltage before energizing the circuit. A master reset establishes an all-zero count, so using it incorrectly during normal operation can clear accumulated state.
Operate the CD4060BE only within its documented 3 V to 18 V supply range. Place a suitable bypass capacitor near VDD and route the return directly to VSS to reduce supply noise on the counter outputs. When replacing CD4060BE with a lower-voltage candidate, check every clock, reset, and output interface because a 3 V change in the maximum supply rating may affect system-level compatibility.
合規資訊
No explicit environmental or material-compliance declarations were identified for the exact CD4060BE ordering code. Confirm current RoHS, REACH, lead-free, halogen-free, and conflict-minerals documentation with the manufacturer before procurement.
