DS90LV047ATM - 400 Mbps Quad LVDS Driver | Texas Instruments
MPN： DS90LV047ATM ✓ 啟用中DS90LV047ATM 概覽
A low-voltage differential line driver is a semiconductor interface device that converts a single-ended logic signal into two complementary, low-amplitude differential outputs. The receiver interprets the voltage difference between those outputs, giving the interface strong noise immunity and reduced EMI radiation. LVDS therefore belongs to the interface IC hierarchy, where differential line drivers connect digital logic, processors, communications equipment, and display systems over balanced connections.
The DS90LV047ATM provides four CMOS driver channels, support for data rates in excess of 400 Mbps, operation associated with a 3 V supply, and LVDS output levels of approximately 350 mV. Its CMOS inputs accept low-voltage TTL/CMOS signals, simplifying connection to standard digital logic. The 16-pin SOIC package supports conventional surface-mount assembly while offering a pin-compatible upgrade path within the DS90LV047A family.
Flow-through differential signaling divides the link into source and destination signal paths and supports point-to-point data transfer. At 200 MHz clock equivalent, the device is appropriate for communications links, industrial data acquisition, instrumentation, and other interfaces where low signal amplitude, high edge rates, and noise rejection are important. The family is also associated with a companion line receiver, providing a complete transmitter-and-receiver approach for balanced links.
Typical uses include point-to-point LVDS interconnects, high-speed digital backplanes, industrial control systems, test equipment, and data-conversion systems. When pairing the driver with a receiver, verify that the receiver supports the same data rate, signaling convention, supply requirements, and termination topology. Cable length, connector geometry, skew, and grounding can materially affect the usable link margin.
Design the interconnect as a controlled-impedance, balanced transmission line and place the driver close to the source device. Follow the manufacturer’s recommended termination and bypass-capacitor arrangements. Account for connector and cable loss, maintain symmetry between differential pairs, and test the assembled link for ringing, common-mode voltage, and differential eye opening at the intended signaling rate.
This page combines manufacturer specifications, package details, compatible family options, and practical interface-design guidance. It also highlights the distinction between a genuine same-footprint replacement and a merely similar LVDS driver, helping engineers shorten component-selection and PCB-qualification work.
直接替換替代品，適用於 DS90LV047ATM — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： DS90LV047ATM （相同外形與佔位） — 差異在於 Package.
DS90LV047ATM/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
DS90LV047ATMTC/NOPB
✅ 直接替換聯絡詢價
查看資料表 →SN65LVDS047
✅ 直接替換📋 參考替代品（不在目錄中）
DS90LV047ATM 規格
| Product Type | Quad differential line driver |
| Number of Driver Channels | 4 channels |
| Logic Family | CMOS |
| Signaling Standard | LVDS |
| Maximum Data Rate | Greater than 400 Mbps |
| Clock Equivalent | Greater than 200 MHz |
| 供應電壓 | 3 V |
| Differential Output Voltage | Approximately 350 mV |
| Input Logic Levels | Low-voltage TTL/CMOS |
| 封裝 | 16-pin SOIC (D) |
| 腳位數 | 16 pins |
| 安裝類型 | Surface mount |
| 工作溫度 | -40 °C to +85 °C |
| Power Dissipation | Ultra-low power operation |
DS90LV047ATM 16-pin soic (d) 腳位配置指南
DS90LV047ATM（16-pin soic (d) 封裝）的腳位配置。 腳位編號、功能與連接圖定義於製造商資料手冊中。請參閱該手冊以取得確切的封裝尺寸與焊接指引。
無詳細腳位定義資料： DS90LV047ATM.
請參閱 資料表 以查看完整腳位配置。
典型應用
DS90LV047ATM 適用於 6 應用s: High-Speed Point-to-Point Data Links, Industrial Control Interfaces, Test and Measurement Equipment, Data Acquisition and Conversion, High-Speed Digital Backplanes, Communications and Network Equipment.
High-Speed Point-to-Point Data Links
The DS90LV047ATM fits point-to-point digital links that require four differential outputs, data rates above 400 Mbps, and low-power LVDS signaling. Each channel converts a low-voltage TTL/CMOS input into an approximately 350 mV differential output, allowing the receiver to detect the signal from its voltage difference rather than from a single conductor referenced to ground. Place the driver near the transmitting device, use a controlled-impedance balanced route, and apply the receiver’s specified termination. The principal benefit is a compact four-channel transmitter with substantially lower output amplitude than conventional single-ended signaling, improving noise immunity and reducing EMI while supporting high edge rates.
推薦
Industrial Control Interfaces
The DS90LV047ATM can support compact high-speed links inside industrial control equipment where controller data must cross a noisy enclosure or backplane without adding excessive power. Its four channels, more-than-400-Mbps operation, 3 V CMOS implementation, and -40 °C to +85 °C rated range align with industrial communication and data-acquisition architectures. Use it for point-to-point transfers between a controller and an external data-acquisition or processing stage, provided the cable and connector can preserve the intended differential impedance. Keep the escape path short, balance the pair geometry, and validate the interface for the system’s EMC and surge requirements rather than relying on the driver rating alone.
推薦
Test and Measurement Equipment
The DS90LV047ATM is appropriate for test and measurement systems that distribute high-speed digital commands or collect parallel data across short, balanced interconnects. Its four independent LVDS channels can reduce the number of packages needed when routing multi-bit parallel information between instrument cards or a controller and a converter. The more-than-400-Mbps rate provides margin for demanding digital test paths, while the approximately 350 mV differential output reduces susceptibility to common-mode noise. The implementation must still account for cable loss, connector transitions, receiver thresholds, and clock skew. Place each differential pair on a continuous impedance-controlled layer and keep return paths continuous to preserve signal integrity.
推薦
Data Acquisition and Conversion
The DS90LV047ATM can transmit digital data from converters, processors, or field-programmable logic to another subsystem in a data-acquisition chassis. Four differential channels support parallel word transport over balanced conductors, and the data-rate capability above 400 Mbps is useful when converter outputs must be transferred without long periods of activity. The low-voltage LVDS interface can improve noise immunity relative to single-ended CMOS signaling, provided the receiver is properly terminated and the PCB implements controlled impedance. Confirm the converter’s output timing, setup and hold requirements, and the clocking relationship between channels. Use matched routing and matched connector transitions to avoid introducing skew between the four differential pairs.
推薦
High-Speed Digital Backplanes
The DS90LV047ATM is suitable for short point-to-point lanes on a high-speed digital backplane when four channels and low signal amplitude are required. LVDS’s differential nature reduces sensitivity to coupled noise, and the DS90LV047ATM’s more-than-400-Mbps capability supports modern control, status, and auxiliary data paths. Backplane implementation still requires careful stack-up selection, continuous reference planes, loss budgeting, and connector modeling. Avoid layer transitions for the differential pairs when possible, and place any termination where the receiver and manufacturer guidance specify it. Verify lane-to-lane skew because four independent outputs do not automatically compensate for unequal trace or connector delays.
推薦
Communications and Network Equipment
The DS90LV047ATM can drive balanced interconnects in communications equipment, including control-plane, line-card, and service-card links that carry high-speed digital traffic. The quad-channel format integrates four differential transmitters into one 16-pin SOIC, while the approximately 350 mV LVDS output helps reduce radiated emissions compared with full-swing single-ended interfaces. Select DS90LV048A or another compatible receiver and design the link around controlled-impedance PCB traces or qualified cable. Pay particular attention to insertion loss, return loss, skew, and grounding between line cards. Qualification should include worst-case temperature, cable length, connector insertion, and simultaneous switching activity across all four channels.
推薦
推薦產品摘要
工程參考資料，適用於 DS90LV047ATM — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | DS90LV047ATM/NOPB | DS90LV047AT | SN65LVDS047 |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 16-SOIC (D) | 16-SOIC (D) - same package | 16-SOIC (D) - same package | 16-SOIC (D) - same package |
| Driver Channels | 4 channels | 4 channels | 4 channels | 4 channels |
| Data Rate | Greater than 400 Mbps | Greater than 400 Mbps | Greater than 400 Mbps | 400 Mbps-class |
主要差異化特點
- Four-channel 400 Mbps-class LVDS integration (對比DS90LV047ATM/NOPB)
- Documented 3 V CMOS and TTL/CMOS input compatibility (對比SN65LVDS047)
- More-than-400-Mbps operation in a 16-pin SOIC (對比DS90LV047AT)
設計說明
Route each LVDS pair as a controlled-impedance differential trace with continuous reference planes. Keep the DS90LV047ATM close to the transmitting device, match the two conductors geometrically, and minimize vias, stubs, and impedance discontinuities. If the link crosses a connector or board boundary, verify return-path continuity and account for connector and cable loss at the intended data rate. Do not convert one leg of the differential pair to single-ended routing.
Use the termination arrangement specified for the selected receiver and channel topology, and inspect the receiver eye, differential voltage, and common-mode voltage at system-level corners. More than 400 Mbps operation gives substantial data-rate capability, but it does not eliminate limitations from skew, reflections, connector transitions, or cable loss. Measure the completed PCB and cable assembly rather than inferring link margin from clock frequency alone.
Place the DS90LV047ATM and its required bypass capacitors close to their respective supply and ground pins. Use a layout that minimizes loop area and maintains uninterrupted ground references beneath and between the differential pairs. The exact capacitor values and placement should follow the Texas Instruments DS90LV047A datasheet layout guidance. Do not add long stubs for test access because a stub can act as an unintended high-frequency antenna.
Do not treat every quad LVDS driver as a drop-in replacement. Before substituting an alternative, verify every pin function, input threshold, differential-output polarity, supply range, propagation delay, enable state, package drawing, and receiver compatibility. The suffix changes within the DS90LV047A family can affect orderable configuration even when the core data rate remains above 400 Mbps. Record the exact approved manufacturer part number on the production BOM.
合規資訊
Compliance declarations for the exact orderable MPN must be confirmed with the manufacturer. AEC-Q100 qualification is not indicated for this interface IC.
