DSPIC33FJ128GP310AT-I/PT - 16-Bit 40 MIPS DSC 128KB Flash | Microchip
MPN： DSPIC33FJ128GP310AT-I/PT ✓ 啟用中DSPIC33FJ128GP310AT-I/PT 概覽
A digital signal controller combines the deterministic control of a microcontroller with the mathematical throughput of a DSP core. In the system hierarchy, the dsPIC33F family sits between general-purpose MCUs (such as the PIC18) and standalone DSPs, making it the natural choice for embedded control loops that also require fast multiply-accumulate operations, filtering, or transform calculations on a single chip.
Key features include a 16-bit modified Harvard architecture core with DSP engine, 32-channel 10-bit/12-bit analog-to-digital converter, multiple UART, SPI, and I2C peripherals with IrDA and LINbus support, DMA controller, I2S audio interface, AC97 support, PWM outputs, and brown-out detect/reset, power-on reset, and watchdog timer for robust operation.
Technically, the device executes most instructions in a single cycle at 40 MIPS, while the DSP engine provides single-cycle MAC with dual operand fetch. The FLASH program memory supports in-circuit serial programming (ICSP) and in-circuit debugging via multiple PGECx/PGEDx pin pairs. Connectivity spans I2C, SPI, UART/USART, IrDA, and LINbus, suiting both sensing and communication roles in one design.
Typical applications include motor control (BLDC, PMSM, FOC), digital power supplies and inverters, industrial automation and sensing nodes, and audio/communication processing where the I2S and AC97 interfaces and ADC throughput are exploited.
Design consideration: all VDD and VSS pins must be connected for reliable operation and programming; omitting even one pin can cause ICSP programming failures, per the manufacturer documentation.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替換替代品，適用於 DSPIC33FJ128GP310AT-I/PT — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： DSPIC33FJ128GP310AT-I/PT （相同外形與佔位） — 差異在於 Package, Packaging, Peripherals, Operating Temperature, Core.
DSPIC33FJ128GP310A-I/PT
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
DSPIC33FJ128GP310A-I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC33FJ128GP310AT-I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC33FJ128GP310AT-E/PT
✅ 直接替換📋 參考替代品（不在目錄中）
DSPIC33FJ256GP310AT-I/PT
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
DSPIC33FJ128GP310AT-I/PT 最大額定值與電氣特性
| Core Architecture | 16-bit dsPIC33F RISC with DSP engine |
| Maximum CPU Speed | 40 MIPS |
| Program Memory Size | 128KB (128K x 8) FLASH |
| RAM Size | 16KB (16K x 8) |
| 供應電壓 | 3.3 V |
| Number of I/O | 85 |
| ADC Channels | 32-channel 10-bit/12-bit |
| Communication Interfaces | I2C, SPI, UART/USART, IrDA, LINbus |
| Audio Interfaces | I2S, AC97 |
| Peripherals | Brown-out Detect/Reset, DMA, POR, PWM, WDT |
| 封裝 | 100-TQFP (12x12 mm) |
| Terminal Pitch | 0.4 mm |
| 安裝類型 | Surface Mount |
| 工作溫度 | -40C to +85C (I grade) |
| Programming / Debug | ICSP via PGECx/PGEDx pairs, in-circuit debugging |
| Packaging | Tape & Reel (T suffix) |
DSPIC33FJ128GP310AT-I/PT 100-tqfp (12x12 mm) 腳位配置指南
DSPIC33FJ128GP310AT-I/PT（100-tqfp (12x12 mm) 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： DSPIC33FJ128GP310AT-I/PT.
請參閱 資料表 以查看完整腳位配置。
典型應用
DSPIC33FJ128GP310AT-I/PT 適用於 6 應用s: BLDC/PMSM Motor Control, Digital Power Supplies and Inverters, Industrial Automation and Sensing Nodes, Audio Processing and Communication Equipment, Embedded Control in Medical and Laboratory Instruments, Automotive-Adjacent and Off-Highway Equipment Control.
BLDC/PMSM Motor Control
The DSPIC33FJ128GP310AT-I/PT fits sensorless and sensored motor control because its 40 MIPS DSP engine executes single-cycle MAC operations for field-oriented control while the 32-channel 10-bit/12-bit ADC samples phase currents at high rates. Dedicated PWM peripherals generate complementary gate drive signals with hardware dead time, and the DMA offloads ADC result movement to keep the current loop deterministic. Placed as the main controller with a gate-driver IC between DSC and power stage, it delivers closed-loop bandwidths of several kHz. The 128KB FLASH accommodates FOC algorithms plus communication stacks without external memory.
推薦
Digital Power Supplies and Inverters
In digital power (LLC, totem-pole PFC, solar inverters), the DSPIC33FJ128GP310AT-I/PT provides the fast, deterministic control needed for peak-current-mode and voltage-mode loops. The 40 MIPS core plus DSP engine executes compensator math in a few microseconds, the high-channel-count ADC enables multi-rail voltage/current telemetry, and PWM peripherals support complementary outputs with dead-band insertion for half-bridge topologies. DMA-driven ADC-to-PWM paths minimize latency between sampling and duty-cycle update. The 3.3V supply simplifies interfacing with isolated feedback and gate-driver circuits, and brown-out and watchdog functions protect against fault conditions.
推薦
Industrial Automation and Sensing Nodes
For factory automation nodes, the DSPIC33FJ128GP310AT-I/PT combines 85 general-purpose I/O lines, multiple UART/SPI/I2C buses with LINbus and IrDA support, and a rich 32-channel ADC for analog sensor aggregation - flow, pressure, temperature - in one controller. The 16KB RAM buffers sensor data while the DMA sustains background transfers, and the I2C/SPI ports interface with external EEPROMs and displays. Industrial 3.3V logic levels and the -40C to +85C industrial temperature grade suit cabinet-mounted and machinery-mounted environments. In-circuit serial programming allows field firmware updates through a single connector without removing the board.
推薦
Audio Processing and Communication Equipment
The device suits audio and communication equipment through its I2S and AC97 interfaces, which connect directly to audio codecs, plus its DSP engine for filtering, equalization, and echo cancellation at 40 MIPS. The 32-channel ADC digitizes line-level and microphone signals, and UART/IrDA links handle telemetry and remote control. In intercom, PA, and conferencing products, the DSC commonly sits between codec ICs and power amplifiers, executing sample-rate processing while managing user-interface I/O. The 128KB FLASH holds multiple algorithm profiles, and DMA keeps audio streams glitch-free by servicing the I2S peripheral without CPU intervention.
推薦
Embedded Control in Medical and Laboratory Instruments
Benchtop medical and laboratory instruments benefit from the DSPIC33FJ128GP310AT-I/PT's combination of precise analog acquisition and deterministic control. The 12-bit ADC mode plus DSP engine supports signal conditioning chains for biosensors and optical measurement front ends, while PWM outputs drive pumps, heaters, and actuators with closed-loop regulation. Multiple UART ports communicate with displays, printers, and host PCs concurrently. The 3.3V supply and surface-mount 100-TQFP suit compact portable instruments, and watchdog, brown-out, and power-on reset functions maintain safe behavior through supply disturbances. ICSP enables firmware field updates during instrument service intervals.
推薦
Automotive-Adjacent and Off-Highway Equipment Control
Although the -I temperature grade is -40C to +85C, the device family serves off-highway equipment, agricultural controllers, and non-passenger-vehicle transport electronics where ambient conditions remain within industrial limits. The LINbus and UART peripherals integrate with vehicle body networks, the 32-channel ADC reads multi-sensor arrays, and the DSP engine runs filtering for noisy analog environments. For applications requiring higher temperature rating, the pin-compatible DSPIC33FJ128GP310AT-E/PT variant extends operation to +125C without PCB changes. The 40 MIPS throughput supports engine-adjacent control loops and display drivers simultaneously within one controller.
推薦
推薦產品摘要
工程參考資料，適用於 DSPIC33FJ128GP310AT-I/PT — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | DSPIC33FJ128GP310A-I/PT | DSPIC33FJ128GP310AT-I/PF | DSPIC33FJ128GP310AT-E/PT | DSPIC33FJ256GP310AT-I/PT |
|---|---|---|---|---|---|
| Package | 100-TQFP (12x12 mm) | 100-TQFP (12x12 mm) - same | 100-TQFP (12x12 mm) - same | 100-TQFP (12x12 mm) - same | 100-TQFP (12x12 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Memory | 128KB (128K x 8) | 128KB | 128KB | 128KB | 256KB |
| ADC | 32-channel 10/12-bit | 32-channel 10/12-bit | 32-channel 10/12-bit | 32-channel 10/12-bit | 32-channel 10/12-bit |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C | -40C to +85C | -40C to +125C (E grade) | -40C to +85C |
| Silicon Revision / Packaging | Original revision, Tape & Reel (/PT) | A-step revision (errata fixed), Tape & Reel | Tape & Reel, tray equivalent /PF | Tape & Reel, extended temp | Tape & Reel, larger flash die |
主要差異化特點
- Current production A-step errata fix availability (對比DSPIC33FJ128GP310A-I/PT)
- Extended temperature margin option (對比DSPIC33FJ128GP310AT-E/PT)
- Memory-identical lower-cost positioning vs larger flash siblings (對比DSPIC33FJ256GP310AT-I/PT)
設計說明
Connect ALL VDD and VSS pins of the DSPIC33FJ128GP310AT-I/PT. Per the Microchip family documentation and the dsPIC33FJ128GP310 development notes, even one unconnected supply pin can cause ICSP programming failures or erratic operation at 40 MIPS. Decouple each VDD pin with a 0.1uF ceramic capacitor placed within 2 mm of the pin, plus one low-ESR bulk capacitor (4.7uF to 10uF) near the device. The 100-TQFP exposed center area should have a solid ground plane beneath for return-path integrity.
The dsPIC33FJ128GP310 provides multiple PGECx/PGEDx pin pairs for ICSP. Per the northernsoftware.com device notes and Microchip documentation, you may use any pair, but ICSPCLK and ICSPDAT must come from the SAME numbered pair - mixing PGEC2 with PGED1 will fail programming. Pick one pair (e.g., PGEC1/PGED1), bring it to a 5-pin or 6-pin programming header early in layout, and keep the traces short. Also reserve the MCLR pin for the programmer with a 10k pull-up to VDD.
When using the 32-channel ADC for motor current sensing, route the ANx inputs away from PWM output traces to prevent switching noise coupling into measurements. Estimated: at 40 MIPS with typical FOC loop rates of 10-20 kHz, ADC sampling should be synchronized to the PWM midpoint to sample current away from switching edges - configure ADC triggered scans via the PWM module rather than free-running sampling. Use the DMA to move results to RAM so the CPU never misses a sample window.
For the 100-TQFP (12x12 mm, 0.4 mm pitch), verify PCB land pattern against the Microchip TQFP footprint before fabrication - 0.4 mm pitch demands precise paste stencil design. Estimated: use 0.1 mm stencil reduction on lead tips to reduce bridging risk in reflow. Keep crystal or internal oscillator routing away from high-current PWM traces, and place the AVDD/AVSS analog supply filtering (ferrite bead plus 0.1uF/1uF) between digital and analog sections for ADC accuracy.
合規資訊
Listed as current RoHS-compliant production part by DigiKey/LCSC as of 2026-09-26. REACH, halogen-free, and conflict minerals status not stated in retrieved distributor snippets - confirm on Microchip environmental documentation.
