JMB585 - PCIe Gen3x2 to 5-Port SATA 6Gb/s Bridge | JMicron
MPN： JMB585 ✓ 啟用中JMB585 概覽
A bridge controller is a specialized interface IC that translates one bus protocol into another, sitting in the storage hierarchy between the host (PCIe root complex) and the storage device layer (SATA/AHCI drives). In a typical PC system, the JMB585 occupies the same role as a chipset-integrated SATA controller: it enumerates as a standard AHCI host, so operating systems treat its ports exactly like native motherboard SATA ports.
Key features include five independent SATA 6Gb/s downstream ports, an upstream PCIe Gen3 x2 (about 2 GB/s) link, native AHCI and legacy IDE mode support, SSD TRIM command pass-through, and Port Multiplier support for expanding beyond five drives. JMicron emphasizes that the device almost fully saturates the PCIe Gen3 x2 line bandwidth, which matters when multiple SSDs are accessed concurrently.
Technically, the JMB585 is highly integrated with JMicron self-designed PCI Express and SATA PHY IP on a single die, eliminating external PHY chips and reducing BOM cost and board area. Firmware operates transparently with in-box AHCI drivers in Linux, Windows, and most UEFI/BIOS implementations, which is why JMB585-based M.2 A+E and M.2 B+M adapter cards are popular in NAS and home-server builds.
Typical applications include M.2-to-5xSATA expansion adapters for NAS servers (TrueNAS, Unraid), desktop storage upgrade cards, embedded x86 platforms such as the ODYSSEY-X86J4105, and industrial storage expansion where driverless AHCI compatibility is required.
A key design consideration: the PCIe Gen3 x2 uplink (approx. 2 GB/s) is shared across all five SATA ports, so total concurrent bandwidth saturates at roughly two SATA SSDs running at full 6Gb/s speed; mechanical HDD workloads are never limited.
This page synthesizes distributor availability, drop-in alternative analysis versus ASMedia ASM1166 and JMB582, and practical design notes not found in the manufacturer datasheet.
直接替換替代品，適用於 JMB585 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： JMB585 （相同外形與佔位） — 差異在於 Package, RoHS Status, Mounting Type, Function, Host Interface.
JMB582
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →ASM1166
✅ 直接替換聯絡詢價
查看資料表 →ASM1064
✅ 直接替換📋 參考替代品（不在目錄中）
JMB585 規格
| 功能 | PCIe to SATA bridge controller |
| Host Interface | PCIe Gen3 x2 |
| Number of SATA Ports | 5 |
| SATA Speed | 6 Gb/s (SATA III) |
| Protocol Support | AHCI, legacy IDE |
| Port Multiplier Support | Yes |
| TRIM Support | Yes (SSD TRIM pass-through) |
| PHY Integration | Integrated PCIe and SATA PHY (JMicron self-designed) |
| Typical Aggregate Bandwidth | Approx. 2 GB/s (PCIe Gen3 x2 line rate) |
| 封裝 | QFN-76 |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | ROHS compliant (per JLCPCB part listing) |
JMB585 qfn-76 腳位配置指南
JMB585（qfn-76 封裝）的腳位配置。 腳位編號、功能與連接圖定義於製造商資料手冊中。請參閱該手冊以取得確切的封裝尺寸與焊接指引。
無詳細腳位定義資料： JMB585.
請參閱 資料表 以查看完整腳位配置。
典型應用
JMB585 適用於 6 應用s: M.2 to SATA NAS Expansion, Home NAS Servers (TrueNAS / Unraid), Embedded x86 Industrial Platforms, Desktop Storage Upgrade Cards, SSD-Backed Surveillance and Appliance Storage, Drive Caddy and Backplane Expansion.
M.2 to SATA NAS Expansion
The JMB585 is the de facto standard controller for M.2 A+E and B+M key adapter cards that add five SATA 6Gb/s ports to motherboards lacking onboard SATA headers. Its AHCI enumeration means TrueNAS, Unraid, and OpenMediaVault detect all five ports with zero driver configuration, and community reports confirm reliable operation under Linux kernel 5.15 and later. Each port delivers SATA III 6Gb/s, and Port Multiplier support allows future expansion beyond five drives. Designers should note the shared PCIe Gen3 x2 uplink (~2 GB/s) is never a bottleneck for HDD arrays, and LED indicators can be wired to the SATA activity pins for drive status feedback.
推薦
Home NAS Servers (TrueNAS / Unraid)
Home-server builders consistently choose JMB585-based cards when motherboards run out of SATA ports, because the chip presents a standard AHCI interface identical to chipset SATA. In Unraid and TrueNAS forum testing, the JMB585 exhibits fewer errors under Linux than competing controllers, though it lacks ASPM so idle power is slightly higher - typically an acceptable trade for HDD-centric arrays where the ~2 GB/s PCIe Gen3 x2 aggregate bandwidth is far above mechanical drive speeds. TRIM pass-through preserves SSD cache performance in hybrid pools, and legacy IDE mode availability helps with unusual or older host firmware.
推薦
Embedded x86 Industrial Platforms
Embedded x86 boards such as the Seeed ODYSSEY-X86J4105 use the JMB585 to expose five SATA ports through an M.2 slot for industrial storage expansion, data loggers, and edge servers. Driverless AHCI enumeration is the decisive advantage: industrial OS images and locked-down firmware can address the ports without vendor driver integration, simplifying certification and long-term maintenance. The QFN-76 single-die integration of PCIe and SATA PHYs keeps the adapter footprint minimal. Designers should verify supply rails and thermal budget from the official datasheet, and account for the shared 2 GB/s uplink when multiple concurrent streams are specified.
推薦
Desktop Storage Upgrade Cards
For desktop PCs, the JMB585 enables low-cost PCIe x2 or M.2-slot cards that add five SATA 6Gb/s ports for additional SSDs and HDDs without chipset limitations. Because the controller enumerates as standard AHCI, BIOS boot from JMB585-attached drives works on most UEFI firmware, allowing OS installation directly on expanded ports. TRIM support keeps attached SATA SSDs performing optimally over time. The practical bandwidth ceiling is approximately two full-speed SATA SSDs (~550 MB/s each) sharing the PCIe Gen3 x2 link, so mixed SSD/HDD configurations deliver the best value; single-drive sequential workloads run at full SATA III speed.
推薦
SSD-Backed Surveillance and Appliance Storage
Surveillance recorders and storage appliances benefit from the JMB585's combination of five ports, TRIM pass-through, and Port Multiplier support. Continuous-write workloads from multiple camera streams are well within the controller's capability because each SATA III port's 6Gb/s far exceeds per-stream recording rates, and the shared PCIe Gen3 x2 uplink (~2 GB/s) accommodates simultaneous multi-drive writes from HDD or mixed-media pools. Standard AHCI enumeration ensures the appliance firmware's storage stack treats JMB585 ports as first-class drives for RAID or ZFS pooling, without vendor-specific driver code to maintain across OS updates.
推薦
Drive Caddy and Backplane Expansion
The JMB585's SATA host supports Port Multiplier, making it suitable for multi-drive backplanes and hot-swap caddies where more than five physical bays must be served from one controller. With a Port Multiplier-capable backplane, a single JMB585 can address additional drive bays beyond its five native ports, an approach used in budget NAS chassis. AHCI-mode TRIM pass-through preserves SSD health in mixed bays. Engineers should size fan cooling for the QFN-76 controller in enclosed bays, confirm backplane multiplier compatibility (not all chipsets support it in AHCI mode), and validate enumerate order under the target operating system before production.
推薦
推薦產品摘要
工程參考資料，適用於 JMB585 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | JMB582 | ASM1166 | ASM1064 |
|---|---|---|---|---|
| Brand | JMicron Technology | JMicron Technology | ASMedia Technology | ASMedia Technology |
| Package | QFN-76 | QFN (same JMicron family) - verify exact pin count for footprint reuse | QFN - different pinout, board respin required | QFN - different pinout, board respin required |
| SATA Ports | 5 | 2 | 6 | 4 |
| Host Interface | PCIe Gen3 x2 (~2 GB/s) | PCIe Gen3 x2 class | PCIe Gen3 x2 | PCIe Gen3 x2 class |
| SATA Speed | 6 Gb/s | 6 Gb/s | 6 Gb/s | 6 Gb/s |
| AHCI / IDE Mode | AHCI + legacy IDE | AHCI + legacy IDE | AHCI (standard enumeration) | AHCI (standard enumeration) |
| TRIM Support | Yes | Yes (same family feature set) | Yes | Yes |
| Linux Kernel Support | In-box AHCI (verified on 5.15) | In-box AHCI | In-box AHCI (5.15+) | In-box AHCI |
主要差異化特點
- Driverless AHCI enumeration across OS and firmware (對比ASM1166)
- Port Multiplier support (對比ASM1064)
- Near-line-rate PCIe Gen3 x2 utilization (對比JMB582)
設計說明
Budget the shared uplink correctly: all five SATA 6Gb/s ports share the PCIe Gen3 x2 link (~2 GB/s aggregate). Designs assuming five SSDs each running at full ~550 MB/s simultaneously will see throttling beyond roughly two concurrent full-speed SSDs. Mechanical HDD arrays are never limited. Also confirm ASPM expectations early - the JMB585 does not support ASPM per community testing, so always-on servers will idle at higher link power than ASM1166 designs.
The JMB585 integrates both PCIe and SATA PHYs, so PCIe Gen3 differential pairs on the upstream side need controlled-impedance (100 ohm differential) routing with length matching, and each SATA lane requires its own differential pair routing with reference ground. Place the 25 MHz-class reference clock circuit per the JMicron datasheet layout guidelines and keep the PHY region clear of switching-regulator noise. Follow the official JMicron datasheet for decoupling network specifics rather than copying adapter-card photographs.
Estimated: typical adapter-card implementations power the JMB585 from the M.2 slot 3.3V rail; five attached spinning HDDs cannot be powered from the slot and require external SATA power feeding only the drive side, with the controller powered from the slot. Verify exact controller supply pins, voltages, and current budget in the official JMicron datasheet before finalizing power-tree design, as the verified public data does not state supply rail specifics.
合規資訊
ROHS compliance indicated by JLCPCB part listing (C2848040). Other compliance attributes not stated in provided data.
