LPC1765FBD100K - 100MHz Cortex-M3 256KB Flash 64KB SRAM MCU | NXP
MPN： LPC1765FBD100K ✓ 啟用中LPC1765FBD100K 概覽
An MCU (microcontroller unit) is a single integrated circuit that bundles a CPU core, program memory, data memory and peripherals into one package. The Cortex-M3 core is a 32-bit ARM architecture with a Harvard-style design, a 3-stage pipeline and deterministic interrupt latency, used inside the wider hierarchy of microcontrollers -> embedded processors -> semiconductors. LPC17xx devices sit between simple 8-bit controllers and higher-end application processors, adding USB, CAN and Ethernet-class connectivity without requiring an external host CPU.
Key features of this part include USB 2.0 Device, Host and OTG support, an 8-channel DMA controller for low-CPU-overhead data movement, four UARTs, two CAN controllers, three SSP/SPI interfaces, three I2C interfaces, I2S, an 8-channel 12-bit ADC, a 10-bit DAC, motor-control PWM, a quadrature encoder interface and four general-purpose timers. A 100 MHz core plus 64 kB SRAM allows protocol stacks, graphics touch handling and real-time control to run from one device.
Architecturally the LPC1765 pairs a 32-bit Cortex-M3 core running from an internal PLL-multiplied clock with a large set of on-chip AMBA peripherals, all reachable over AHB/APB buses. The on-chip DMA engine moves ADC samples, USB traffic and display data without involving the CPU, which is what keeps real-time loops deterministic. Power management supports low-power sleep and deep-sleep states for battery-backed designs.
Typical applications include industrial data acquisition and PLC-type controllers, USB-to-serial bridges and protocol converters, CAN-based automotive and machine-control nodes, HMI panels with touch and display interfaces, USB-connected test and measurement equipment, and networked embedded gateways using an external Ethernet PHY.
When designing around this MCU, match crystal and decoupling requirements to the NXP reference design, keep USB impedance-controlled traces at 90 ohm differential and provide a clean 3.3 V rail with bulk plus high-frequency decoupling. Check the maximum I/O current per port pin before driving relays or LED strings.
This page brings together the manufacturer feature set, drop-in alternatives within the same LQFP-100 footprint, and practical layout and power guidance that a datasheet alone does not present in one place.
直接替換替代品，適用於 LPC1765FBD100K — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LPC1765FBD100K （相同外形與佔位） — 差異在於 Package, Quadrature Encoder Interface, Flash Memory, Product Type, DAC.
LPC1766FBD100
✅ 直接替換聯絡詢價
查看資料表 →LPC1763FBD100Y
✅ 直接替換聯絡詢價
查看資料表 →LPC1768FBD100K
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →LPC1764FBD100K
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →LPC1758FBD100
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LPC1765FBD100K 最大額定值與電氣特性
| Core | ARM Cortex-M3, 32-bit |
| Maximum CPU Frequency | 100 MHz |
| Flash Memory | 256 kB |
| SRAM | 64 kB |
| 封裝 | LQFP-100 (14 x 14 mm) |
| Number of I/O | 70 |
| 供應電壓 | 3.3 V |
| 工作溫度 | -40 C to +85 C |
| USB | USB 2.0 Device, Host and OTG |
| DMA Channels | 8 |
| UART | 4 |
| CAN Controllers | 2 |
| SSP / SPI Interfaces | 3 |
| I2C Interfaces | 3 |
| ADC | 8-channel, 12-bit |
| DAC | 10-bit |
| I2S Interface | Yes |
| Timers | 4 general-purpose timers plus motor-control PWM |
| Quadrature Encoder Interface | Yes |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
LPC1765FBD100K lqfp-100 (14 x 14 mm) 腳位配置指南
LPC1765FBD100K（lqfp-100 (14 x 14 mm) 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： LPC1765FBD100K.
請參閱 資料表 以查看完整腳位配置。
典型應用
LPC1765FBD100K 適用於 6 應用s: Industrial Data Acquisition and Control Node, USB-to-Serial Bridge and Protocol Converter, CAN-Based Automotive and Machine Control, Human-Machine Interface with Touch and Display, USB-Connected Test and Measurement Equipment, Connected Embedded Gateway with Ethernet.
Industrial Data Acquisition and Control Node
The LPC1765FBD100K suits measurement and control nodes that must combine fast analog sampling with several fieldbus links. Its 8-channel 12-bit ADC can be triggered by timers and moved by the 8-channel DMA engine without loading the CPU, while two CAN controllers and four UARTs cover bus segmentation on the same board. At 100 MHz the Cortex-M3 core has ample headroom for filtering, unit conversion and a supervisory loop. The -40 C to +85 C rating and 70 GPIO in LQFP-100 fit typical industrial control cabinet environments where a small package and long availability are valued.
推薦
USB-to-Serial Bridge and Protocol Converter
A USB Device, Host and OTG capable Cortex-M3 with 64 kB of SRAM makes the LPC1765FBD100K a natural fit for USB-to-UART, USB-to-RS-485 and USB-to-CAN gateways. The dedicated USB controller plus DMA support sustained data rates while the four UARTs and two CAN channels expose legacy industrial ports to a single USB connection. Firmware can enumerate as CDC-ACM, HID or a vendor-specific class, and the 256 kB of flash accommodates protocol translation tables. The LQFP-100 package also leaves room for galvanic isolation components alongside the transceiver.
推薦
CAN-Based Automotive and Machine Control
Two integrated CAN controllers, motor-control PWM with position capture and a quadrature encoder interface give the LPC1765FBD100K the control primitives needed for machine and vehicle subsystems. The 100 MHz Cortex-M3 core handles the higher-level control algorithm while the PWM and encoder blocks deliver deterministic timing in hardware. With -40 C to +85 C operation and a 14 x 14 mm LQFP-100 footprint, the part fits space-constrained control electronics. Adding a standalone Ethernet PHY option also allows the same hardware platform to report diagnostics upward.
推薦
Human-Machine Interface with Touch and Display
The LPC1765FBD100K powers compact HMI panels that combine a display, capacitive or resistive touch controller and a few sensors. Three I2C ports and three SSP/SPI ports address touch controllers, SPI displays and external flash simultaneously, while I2S supports digital audio codecs for status tones or voice prompts. The 8-channel 12-bit ADC and 10-bit DAC can serve analog sensor inputs and a reference or control output. The 8-channel DMA engine refreshes display and touch buffers with minimal CPU intervention, which keeps the interface responsive under multitasked operation.
推薦
USB-Connected Test and Measurement Equipment
The combination of a 100 MHz Cortex-M3 core, USB 2.0 and an 8-channel 12-bit ADC makes the LPC1765FBD100K well suited to handheld or benchtop instruments that stream samples to a host PC. DMA transfers captured ADC data straight from the peripheral into SRAM buffers while the core formats packets, and the four UARTs and three SSP/SPI ports drive external front-end components, relays or reference sources. The 64 kB of SRAM accommodates double buffering, and the 256 kB of flash holds calibration tables and USB descriptors.
推薦
Connected Embedded Gateway with Ethernet
For gateways that bridge field buses to a network, the LPC1765FBD100K provides the local processing and USB capability while an external PHY adds Ethernet. The Cortex-M3 handles protocol translation between two CAN or UART links and the network stack, and the on-chip DMA keeps Ethernet traffic from stalling the real-time control loop. The 256 kB flash and 64 kB SRAM are adequate for a lightweight TCP/IP stack plus buffering, and the LQFP-100 package keeps the board compact. The same platform can also serve as a USB-to-Ethernet adapter during commissioning.
推薦
推薦產品摘要
工程參考資料，適用於 LPC1765FBD100K — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LPC1766FBD100 | LPC1763FBD100Y | LPC1768FBD100 | LPC1764FBD100 | LPC1758FBD100 |
|---|---|---|---|---|---|---|
| Package | LQFP-100 (14 x 14 mm) | LQFP-100 (14 x 14 mm) - same | LQFP-100 (14 x 14 mm) - same | LQFP-100 (14 x 14 mm) - same | LQFP-100 (14 x 14 mm) - same | LQFP-100 (14 x 14 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core | ARM Cortex-M3, 32-bit | ARM Cortex-M3, 32-bit | ARM Cortex-M3, 32-bit | ARM Cortex-M3, 32-bit | ARM Cortex-M3, 32-bit | ARM Cortex-M3, 32-bit |
| Maximum CPU Frequency | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Flash Memory | 256 kB | 512 kB | 256 kB | 512 kB | 256 kB | 256 kB |
| SRAM | 64 kB | 64 kB | 64 kB | 64 kB | 64 kB | 32 kB |
| USB Support | USB 2.0 Device, Host and OTG | USB 2.0 Device, Host and OTG | USB present, reduced feature set | USB 2.0 Device, Host and OTG | Reduced USB/CAN feature set | No USB, fewer peripherals |
| CAN Controllers | 2 | 2 | Reduced CAN feature set | 2 | Reduced CAN feature set | Reduced CAN feature set |
| Ethernet MAC | No (external PHY required) | No (external PHY required) | No | Yes, on-chip Ethernet MAC | No | No |
| Number of I/O | 70 | 70 | Reduced | 70 | Reduced | Reduced |
主要差異化特點
- Balanced memory and peripheral set at 256 kB flash with USB, dual CAN and 64 kB SRAM (對比LPC1758FBD100)
- Straightforward memory upgrade path without a PCB change (對比LPC1766FBD100)
- Adds Ethernet MAC in the same socket when networking is required (對比LPC1764FBD100)
- Larger general-purpose peripheral complement than the reduced-variant parts (對比LPC1763FBD100Y)
設計說明
Decoupling is the single highest-leverage layout decision for a 100 MHz Cortex-M3 design. Place a 100 nF ceramic capacitor at every VDD pin with the shortest possible via connection to the ground plane, and add a bulk 4.7 uF to 10 uF ceramic capacitor near the regulator output. Keep the supply loop area minimal because the internal PLL multiplies the crystal reference and supply noise at 100 MHz translates directly into clock jitter and jitter-induced EMI.
Route USB D+ and D- as a 90 ohm differential pair with continuous reference plane underneath, matched length within 0.5 mm, and no stubs or test pads on the pair. The LQFP-100 footprint leaves only 0.5 mm pitch, so consider a fine-pitch PCB with filled and capped vias directly beneath the device. Keep the crystal loop small, guard it with ground on three sides, and keep switching regulators and their inductors away from the oscillator and ADC input traces.
The 8-channel 12-bit ADC is fed by the same supply rail as the 100 MHz core, so analog inputs will pick up switching and digital crosstalk unless the layout separates them. Route analog traces on a quiet inner layer referenced to a solid ground plane, place an RC anti-alias filter at the pin, and connect the ADC reference pin to a local bypass capacitor. If the application measures microvolt-level signals, add an external instrumentation amplifier instead of relying on the on-chip converter.
Two mistakes account for most first-board failures with this MCU. First, the 3.3 V rail must reach the specified tolerance during the PLL lock sequence, so allow for startup current steps and provide bulk capacitance. Second, several pins are multifunction, and using a pin for its secondary function without checking the pin connect table can silently disable the primary function such as a timer capture or debug output. Always reconcile the schematic against the pin description table before layout release.
合規資訊
RoHS compliance is indicated for the LPC1765FBD100 part listing. The manufacturer publishes environmental quality and shipping information for the LPC1765FBD100 product page; REACH, halogen-free status and conflict-minerals declarations are not stated in the available product information.
