LTC2162IUK - 16-Bit 65Msps Low Power ADC | Analog Devices
MPN： LTC2162IUK ✓ 啟用中LTC2162IUK 概覽
What is a pipelined ADC: A pipelined analog-to-digital converter is a multi-stage sampling converter that processes analog input through a cascade of low-resolution flash stages and a digital error-correction back end. Pipelined ADCs sit within the hierarchy of Nyquist ADCs and offer the best trade-off between sample rate, resolution, and power consumption, making them the workhorse of communications infrastructure, test instrumentation, and software-defined radio.
The converter integrates a single differential input channel, an internal reference, and configurable digital outputs ranging from CMOS/LVDS parallel to serial SPI/LVDS, allowing direct interface to FPGAs, DSPs, and ASICs. Differential analog inputs (1 Vp-p or 2 Vp-p) feed an internal sample-and-hold, simplifying front-end design. Maximum power dissipation is approximately 140 mW at 65 Msps with CMOS output, suiting thermally constrained dense boards.
The integrated bandgap reference, clock duty-cycle stabilizer, and programmable digital gain/offset calibration remove the need for external circuitry in many applications. Internal reference can also be overdriven for best gain-drift performance in instrumentation.
Typical applications include communications receivers, software-defined radio (SDR), basestation IF sampling, portable instrumentation, ultrasound imaging front ends, and multichannel data-acquisition systems. The wide input bandwidth (>300 MHz differential) also supports direct IF sampling of cellular and cable-infrastructure signals.
When designing with this device, ensure the analog input common-mode bias is well-bypassed and that the exposed pad is soldered to a low-impedance ground plane for thermal relief. The internal duty-cycle stabilizer removes the need for an external clock jitter-cleaner at sample rates up to 65 Msps, but upstream PLL jitter still degrades SNR.
This page synthesizes authorized distributor pricing, pin-to-pin drop-in alternatives within the QFN-52 footprint, and practical PCB-layout guidance not consolidated in the manufacturer datasheet, helping engineers choose between the LTC2162, LTC2161, and LTC2160 speed grades with full design context.
直接替換替代品，適用於 LTC2162IUK — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
LTC2162IUK#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2162IUK#TRPBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2161IUK
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LTC2160IUK
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LTC2162CUK
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2192IUKG#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2162IUK 最大額定值與電氣特性
| 解析度 | 16 bit |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Sample Rate (Max) | 65 Msps |
| Input Type | Differential (Pseudo-Differential) |
| 輸入電壓範圍 | 1 Vp-p or 2 Vp-p |
| Analog Supply Voltage | 1.7 V to 1.9 V |
| Digital Output Supply | 1.1 V to 1.9 V (CMOS/LVDS selectable) |
| SNR | 77 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Digital Output Interface | Parallel CMOS / Parallel LVDS / Serial SPI / Serial LVDS |
| Reference | Internal (with external override) |
| 工作溫度 | -40C to +85C (Industrial) |
| 封裝 | 52-lead 7x7 mm QFN-EP (UK package) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant (PBF suffix per DigiKey listing) |
LTC2162IUK 腳位配置
| 腳位 1 | VREF — Reference voltage bypass |
| 腳位 2 | GND — Ground |
| 腳位 3 | AIN+ — Differential analog input (positive) |
| 腳位 4 | AIN- — Differential analog input (negative) |
| 腳位 5 | GND — Ground |
| 腳位 6 | GND — Ground |
| 腳位 7 | ENC+ — Encode clock input (positive) |
| 腳位 8 | ENC- — Encode clock input (negative) |
| 腳位 9 | GND — Ground |
| 腳位 10 | OVL — Overflow/overrange indicator |
| 腳位 11 | D15/D0/CKOUT — Parallel data bit 15 / serial data output / clock out (mode dependent) |
| 腳位 12 | D14/D1/FRAME — Parallel data bit 14 / serial framing |
| 腳位 13 | D13/D2/BTX+ — Parallel data bit 13 / serial LVDS BTX positive |
| 腳位 14 | D12/D3/BTX- — Parallel data bit 12 / serial LVDS BTX negative |
| 腳位 15 | D11 — Parallel data bit 11 |
| 腳位 16 | D10 — Parallel data bit 10 |
| 腳位 17 | D9 — Parallel data bit 9 |
| 腳位 18 | D8 — Parallel data bit 8 |
| 腳位 19 | OGND — Output driver ground |
| 腳位 20 | OVDD — Output driver supply |
| 腳位 21 | OE — Output enable (active high) |
| 腳位 22 | OF — Output format select |
| 腳位 23 | CS — Chip select for SPI mode |
| 腳位 24 | SCK — SPI serial clock input |
| 腳位 25 | SDI — SPI serial data input |
| 腳位 26 | SDO — SPI serial data output |
| 腳位 27 | GAIN — Programmable analog input gain |
| 腳位 28 | VCM — Common-mode voltage bypass |
| 腳位 29 | GND — Ground |
| 腳位 30 | AVDD — Analog 1.8 V supply |
| 腳位 31 | GND — Ground |
| 腳位 32 | GND — Ground |
| 腳位 33 | AVDD — Analog 1.8 V supply |
| 腳位 34 | GND — Ground |
| 腳位 35 | GND — Ground |
| 腳位 36 | D7 — Parallel data bit 7 |
| 腳位 37 | D6 — Parallel data bit 6 |
| 腳位 38 | D5 — Parallel data bit 5 |
| 腳位 39 | D4 — Parallel data bit 4 |
| 腳位 40 | D3 — Parallel data bit 3 |
| 腳位 41 | D2 — Parallel data bit 2 |
| 腳位 42 | D1 — Parallel data bit 1 |
| 腳位 43 | D0 — Parallel data bit 0 |
| 腳位 44 | DRVDD — Digital output driver supply |
| 腳位 45 | GND — Ground |
| 腳位 46 | DNC — Do not connect |
| 腳位 47 | DNC — Do not connect |
| 腳位 48 | DNC — Do not connect |
| 腳位 49 | DNC — Do not connect |
| 腳位 50 | GND — Ground |
| 腳位 51 | GND — Ground |
| 腳位 52 | DGND — Digital core ground |
| 腳位 53 | EP — Exposed thermal pad - must be soldered to ground plane |
典型應用
LTC2162IUK 適用於 6 應用s: Software-Defined Radio (SDR) Receiver, Cellular Base Station IF Sampling, Portable Test and Measurement Instrumentation, Ultrasound Imaging Front End, Wideband Data Acquisition Systems, Communications Test Equipment.
Software-Defined Radio (SDR) Receiver
The LTC2162IUK delivers 65 Msps throughput with 90 dB SFDR and 0.07 ps RMS aperture jitter, which are the three parameters that determine whether an ADC can undersample a wide-bandwidth IF signal without introducing aliasing artifacts. Placed between the RF front-end mixer and the FPGA DSP pipeline, it captures intermediate-frequency signals up to several hundred MHz directly, eliminating a second downconversion stage and shrinking the RF signal chain.
推薦
Cellular Base Station IF Sampling
Cellular baseband receivers benefit from the LTC2162IUK's 77 dB SNR, which directly sets the receiver's EVM noise floor under processing gain. Mounted on the LTE or 5G-NR receiver card, it digitizes a 30-200 MHz IF after the SAW filter, allowing the remaining demodulation to occur in the FPGA. Differential 1 Vp-p or 2 Vp-p input ranges let designers trade dynamic range for noise figure via front-end attenuator settings.
推薦
Portable Test and Measurement Instrumentation
The LTC2162IUK's combination of 16-bit resolution, 65 Msps sample rate, and sub-200 mW power dissipation suits handheld oscilloscope, spectrum analyzer, and signal-analyzer front ends. Designers can place it directly after the input attenuator and antialias filter to capture 30 MHz bandwidth signals in field instruments. Industrial -40C to +85C operation supports outdoor or factory-floor deployments.
推薦
Ultrasound Imaging Front End
In medical and industrial ultrasound systems, the LTC2162IUK is positioned after the TGC (time-gain control) amplifier and immediately ahead of the beamforming FPGA, providing 65 Msps to capture RF echo returns spanning several harmonics of the fundamental transmit frequency. Its 77 dB SNR maintains 12+ effective bits at the imaging chain output, which directly translates into diagnostic dynamic range and depth-of-penetration.
推薦
Wideband Data Acquisition Systems
The LTC2162IUK adds 65 Msps of precision to multi-channel data-acquisition cards, capturing transient and vibration data in motors, turbines, and aerospace test rigs. Differential analog inputs reject common-mode noise picked up by long sensor cables, and the integrated bandgap reference removes the requirement for an external precision reference at moderate temperature ranges.
推薦
Communications Test Equipment
Communications testers (vector signal analyzers, signal generators, multisimulator test benches) use the LTC2162IUK to digitize standards-compliant waveforms such as LTE, 5G NR, and DOCSIS 3.1. Its 90 dB SFDR keeps modulation sidebands visible up to high input frequencies, while LVDS output modes reduce EMI by switching the data bus at controlled edges.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2162IUK — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2162IUK#PBF | LTC2162IUK#TRPBF | LTC2161IUK | LTC2162CUK | LTC2192IUKG#PBF |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-lead QFN-EP (UK) | 52-lead QFN-EP (UK) | 52-lead QFN-EP (UK) | 52-lead QFN-EP (UK) | 52-lead QFN-EP (UK) | 52-lead QFN-EP (UK) |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | |
| Sample Rate | 65 Msps | 65 Msps | 40 Msps | 65 Msps | 65 Msps | |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C | 0C to +70C (Commercial) | -40C to +85C | |
| RoHS Status | Yes (with #PBF suffix) | RoHS compliant | RoHS compliant | Per suffix (#PBF) | Per suffix (#PBF) |
主要差異化特點
- Highest-speed member of the LTC2160/2161/2162 pin-compatible family (對比LTC2161IUK (40 Msps))
- Industrial operating temperature for outdoor/cabinet use (對比LTC2162CUK (Commercial grade))
- Fully differential 1 Vp-p or 2 Vp-p input with internal duty-cycle stabilizer (對比LTC2192IUKG#PBF (14-bit variant))
設計說明
Estimated: The exposed thermal pad (pin 53) must be soldered to a continuous low-impedance ground plane to meet the specified AC performance. Use at least 8 thermal vias under the pad (0.3 mm drill, 1.0 mm pitch) to a ground pour on layer 2. Missing thermal vias increase junction temperature by 15C, which can degrade SNR by 0.5 dB. Place 0.1 uF decoupling within 3 mm of every AVDD and DRVDD pin, and 10 uF bulk capacitors at each corner of the analog supply island.
Estimated: Clock source integrity is the single largest contributor to ADC SNR degradation. The 0.07 ps RMS aperture jitter budgets only ~250 fs of upstream clock jitter at 65 Msps; a noisy FPGA-PLL output with 2 ps RMS jitter will reduce SNR by ~10 dB. Use a dedicated low-jitter clock generator (such as AD9516 or AD9523) or a narrow-band jitter-cleaning PLL between the system clock and the ENC+/ENC- inputs. Enable the internal duty-cycle stabilizer to compensate for clock asymmetry up to 65 Msps.
Differential input traces must be length-matched within 0.5 mm to preserve the differential balance and 90 dB SFDR. Route the AIN+/AIN- pair on a 100 ohm differential impedance strip with ground-side shielding. Avoid routing over split planes; the QFN exposed pad requires a continuous ground flood underneath. For LVDS output modes, place 100 ohm differential terminations within 5 mm of the FPGA receiver pins.
Estimated: Isolate the analog AVDD (pin 30, 33) and digital DRVDD (pin 44) power islands using ferrite beads to prevent digital switching noise from coupling back into the analog front end. The data bus D0-D15 (pins 11-18, 36-43) is a high-current switching source that can corrupt the analog supply if not adequately filtered. Route all data and clock signals on the opposite side of the PCB from the analog inputs to minimize crosstalk.
合規資訊
RoHS compliance confirmed by DigiKey listing for the LTC2162IUK#PBF variant. AEC-Q100 not applicable (industrial grade only). Conflict-minerals compliance follows Analog Devices standard policy.
