LTC2268IUJ-14 - 14-Bit 125Msps Dual ADC, LVDS | Analog Devices
MPN： LTC2268IUJ-14 ✓ 啟用中LTC2268IUJ-14 概覽
A pipelined ADC is a high-speed successive-stage converter architecture in which each clock cycle advances the sampled signal through low-resolution flash stages, producing N bits of resolution at sample rates from tens to hundreds of Msps. Pipelined ADCs sit within the broader data-converter hierarchy (ADC -> Nyquist-rate ADC -> high-speed converter -> mixed-signal IC) and are the workhorse of communications, instrumentation, and imaging front ends where multi-channel simultaneity, wide analog bandwidth, and serial LVDS output are required to feed an FPGA or ASIC.
Key features include an 800 MHz full-power sample-and-hold bandwidth, 73 dB SNR and 90 dB SFDR at baseband (typical), 2-lane LVDS serialization configurable to 16-, 14-, or 12-bit framing, pin-compatible 14-bit and 12-bit family members, and shutdown plus nap modes for power-sensitive designs. The serial LVDS interface minimizes data-line count and FPGA pin usage, while SPI-port configuration allows flexible output formatting per channel.
Typical applications include cellular base-station receivers, diversity radio, test and measurement instrumentation, digital predistortion feedback paths, medical imaging front-ends, and multi-channel data-acquisition cards. Per the manufacturer datasheet, the LTC2268-14 family starts from $79.69 per 1k unit, with the LTC2268IUJ-14#PBF version offered by authorized distributors including DigiKey and Mouser.
When designing in this part, observe the differential-input common-mode requirement and place 0.1 µF bypass capacitors as close as possible to each supply pin with a larger bulk capacitor on the analog AVDD rail. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and low-inductance return. LVDS trace length matching and 100 Ω differential termination are critical to preserve signal integrity at 125 Msps.
This page synthesizes distributor pricing, pin-compatible family alternatives, and practical PCB-layout guidance not found in the manufacturer datasheet alone.
直接替換替代品，適用於 LTC2268IUJ-14 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2268IUJ-14 （相同外形與佔位） — 差異在於 Package, Operating Temperature Range, Number of Channels, Resolution, RoHS Status.
LTC2268IUJ-14#TRPBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2267IUJ-14
✅ 直接替換聯絡詢價
查看資料表 →LTC2266IUJ-14
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2268IUJ-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2264IUJ-14
✅ 直接替換聯絡詢價
查看資料表 →LTC2268IUJ-14 最大額定值與電氣特性
| 解析度 | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 125 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| Digital Output Interface | Serial LVDS (2-lane / 1-lane modes) |
| Analog Supply Voltage | 1.7 V to 1.9 V |
| Digital Supply Voltage | 1.7 V to 1.9 V |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| SNR (typical) | 73 dB |
| SFDR (typical) | 90 dB |
| Full-Power Bandwidth | 800 MHz |
| Missing Codes | None over temperature |
| Shutdown/Nap Modes | Yes |
| SPI Configuration Port | Yes (serial) |
| 封裝 | 40-QFN (6x6 mm) with exposed pad |
| 工作溫度範圍 | -40 °C to +85 °C (industrial) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant (PBF suffix) |
LTC2268IUJ-14 腳位配置
| 腳位 1 | INA+ — Channel A positive differential analog input |
| 腳位 2 | INA- — Channel A negative differential analog input |
| 腳位 3 | INB+ — Channel B positive differential analog input |
| 腳位 4 | INB- — Channel B negative differential analog input |
| 腳位 5 | VCM — Common-mode voltage output (bias for inputs) |
| 腳位 6 | REFT — Internal reference top decoupling |
| 腳位 7 | REFB — Internal reference bottom decoupling |
| 腳位 8 | AVDD — Analog 1.8 V supply |
| 腳位 9 | GND — Analog ground |
| 腳位 10 | SENSE — Reference sense pin (internal/external reference select) |
| 腳位 11 | GND — Analog ground |
| 腳位 12 | AVDD — Analog 1.8 V supply |
| 腳位 13 | CLK+ — Differential clock input positive |
| 腳位 14 | CLK- — Differential clock input negative |
| 腳位 15 | GND — Digital ground |
| 腳位 16 | DVDD — Digital 1.8 V supply |
| 腳位 17 | OF_A — Channel A overflow / out-of-range LVDS flag |
| 腳位 18 | OF_B — Channel B overflow / out-of-range LVDS flag |
| 腳位 19 | GND — Digital ground |
| 腳位 20 | SDO — SPI serial data output |
| 腳位 21 | SDI — SPI serial data input |
| 腳位 22 | SCK — SPI serial clock input |
| 腳位 23 | CS — SPI chip select (active low) |
| 腳位 24 | MODE — Output mode select (1-lane/2-lane LVDS) |
| 腳位 25 | GND — Digital ground |
| 腳位 26 | DA0_A+ — Channel A LVDS data lane 0 positive |
| 腳位 27 | DA0_A- — Channel A LVDS data lane 0 negative |
| 腳位 28 | DA1_A+ — Channel A LVDS data lane 1 positive |
| 腳位 29 | DA1_A- — Channel A LVDS data lane 1 negative |
| 腳位 30 | GND — Digital ground |
| 腳位 31 | DA0_B+ — Channel B LVDS data lane 0 positive |
| 腳位 32 | DA0_B- — Channel B LVDS data lane 0 negative |
| 腳位 33 | DA1_B+ — Channel B LVDS data lane 1 positive |
| 腳位 34 | DA1_B- — Channel B LVDS data lane 1 negative |
| 腳位 35 | GND — Digital ground |
| 腳位 36 | FR+ — Frame LVDS output positive |
| 腳位 37 | FR- — Frame LVDS output negative |
| 腳位 38 | CLKOUT+ — LVDS clock output positive |
| 腳位 39 | CLKOUT- — LVDS clock output negative |
| 腳位 40 | SHDN — Shutdown/nap mode control |
典型應用
LTC2268IUJ-14 適用於 6 應用s: Cellular Base-Station Receiver, Diversity Radio Receiver, Test and Measurement Instrumentation, Digital Predistortion Feedback Path, Medical Imaging Front-End, Multi-Channel Data Acquisition Card.
Cellular Base-Station Receiver
The LTC2268IUJ-14's 125 Msps per-channel sample rate, dual simultaneous-sampling channels, and 800 MHz full-power bandwidth make it ideal for cellular base-station receiver paths. Two channels support main and diversity antenna digitization with 73 dB SNR and 90 dB SFDR preserving signal integrity through the analog front end. The serial LVDS output minimizes FPGA pin count, while 1.7 V to 1.9 V supplies align with modern base-station SoC platforms. Per Analog Devices datasheet, the wide analog input bandwidth allows direct IF sampling without external downconversion stages.
推薦
Diversity Radio Receiver
Diversity-radio front ends require two tightly synchronized ADC channels to capture orthogonal antenna signals. The LTC2268IUJ-14's simultaneous-sampling dual-channel architecture provides matched sample timing across both channels, with ±0.3 LSB DNL and 1.2 LSB RMS transition noise preserving signal fidelity across both antenna paths. The 73 dB SNR supports 3G/4G/5G demodulation chains while the 40-QFN (6x6) exposed-pad package enables compact PCB layouts with good thermal performance for outdoor radio units.
推薦
Test and Measurement Instrumentation
Test and measurement equipment such as oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers benefit from the LTC2268IUJ-14's 800 MHz full-power bandwidth and 90 dB SFDR. The 14-bit resolution and ±1 LSB INL provide measurement accuracy required for validating RF and mixed-signal designs, while dual channels enable two-probe simultaneous acquisition. SPI-port configuration allows mode changes on the fly, supporting adaptive bandwidth/resolution trade-offs per measurement channel without PCB rework.
推薦
Digital Predistortion Feedback Path
Digital predistortion (DPD) systems in modern power amplifiers capture the output spectrum and feed back to the digital signal processor for distortion correction. The LTC2268IUJ-14's 800 MHz bandwidth digitizes multiple carrier harmonics simultaneously, while its 73 dB SNR preserves the small intermodulation components that drive the DPD correction algorithm. Dual channels allow observation of both forward and reverse-path signals with matched timing, and the low power consumption suits densely populated multi-transmitter line cards.
推薦
Medical Imaging Front-End
Ultrasound and other medical imaging modalities require multiple synchronized receive channels with high dynamic range. The LTC2268IUJ-14's two simultaneous-sampling channels support phased-array beamforming front ends, with 73 dB SNR preserving weak echo returns and 90 dB SFDR rejecting strong off-axis signals. The 40-QFN (6x6) package footprint allows compact probe-head and bedside-monitor designs, while the industrial -40 °C to +85 °C temperature range supports a wide range of clinical environments without additional thermal conditioning.
推薦
Multi-Channel Data Acquisition Card
PCIe and PXIe data-acquisition cards stack multiple ADC channels for sonar, vibration analysis, and industrial inspection. The LTC2268IUJ-14's dual-channel 125 Msps architecture doubles channel density per board, while the serial LVDS interface reduces FPGA I/O pin requirements - critical when aggregating 16 or 32 channels on a single board. Per the Analog Devices datasheet, pin compatibility with 105 Msps (LTC2267) and 80 Msps (LTC2266) variants lets designers offer multi-speed product SKUs from a single PCB layout.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2268IUJ-14 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2268IUJ-14#TRPBF | LTC2267IUJ-14 | LTC2266IUJ-14 | LTC2268IUJ-12 | LTC2264IUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) with exposed pad | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit | 14 bit |
| Sample Rate | 125 Msps | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 40 Msps |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 | 2 |
| Supply Voltage | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V | 1.7 V to 1.9 V |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| 1k Unit Price (USD, approx.) | $79.69 | $79.69 | Lower (105 Msps) | Lower (80 Msps) | Lower (12-bit) | Lower (40 Msps) |
主要差異化特點
- Pin compatibility across the LTC2268/67/66 14-bit and 12-bit family (對比LTC2268IUJ-12)
- Highest sample rate in the 14-bit QFN-40 family (對比LTC2267IUJ-14)
- Serial LVDS interface reduces FPGA pin count (對比CMOS-parallel-output ADCs)
設計說明
The 40-QFN (6x6) exposed pad must be soldered to a continuous, unbroken ground plane on the top PCB layer for low-inductance return currents and thermal dissipation. Place 0.1 µF X7R ceramic bypass capacitors within 2 mm of every AVDD and DVDD pin, and add a 10 µF tantalum or ceramic bulk capacitor on each supply rail near the package. Keep digital LVDS output traces length-matched within 1 mm and 100 Ω differentially terminated at the receiver.
Route the LVDS output pairs (DA0_A, DA1_A, DA0_B, DA1_B, FR, CLKOUT) on a dedicated inner PCB layer with a continuous ground reference plane and 100 Ω differential impedance. Avoid routing LVDS over plane splits or noisy supply regions. Maintain intra-pair length matching within 0.5 mm and inter-pair matching within 1 mm to preserve data-eye margin at 125 Msps.
Do not float the SENSE pin - it must be tied to AVDD for internal reference mode or to an external reference for custom full-scale settings. The CLK+ and CLK- differential clock must meet the datasheet-specified common-mode and amplitude requirements; a single-ended clock source requires an external balun or transformer. Ensure the SPI CS pin is held high during normal operation to prevent accidental register writes that could change output mode or shutdown state.
Sequence AVDD before DVDD by at least 1 ms per Analog Devices application guidance, or use the SHDN pin to gate digital outputs until analog supplies are stable. This prevents spurious LVDS outputs and latch-up risk. The shutdown mode reduces supply current to microampere range; the nap mode reduces sample-clock internal activity for partial power saving. Both modes preserve register configuration per the datasheet.
合規資訊
RoHS and REACH compliance per the #PBF suffix designation and the ETEI comparison data. AEC-Q100 not applicable - this part is not automotive qualified.