LTC2293CUP - Dual 12-Bit 65Msps Low Power 3V ADC | Analog Devices
MPN： LTC2293CUP ✓ 啟用中LTC2293CUP 概覽
A pipelined ADC (pipelined analog-to-digital converter) is a multi-stage converter architecture that processes the analog input through successive low-resolution flash sub-ADC stages, with each stage driving an inter-stage DAC and residue amplifier. Pipelined ADCs are favored for high sample rates (10 Msps to >1 Gsps) and resolutions from 8 to 16 bits because they balance speed, latency, and active power far better than flash or successive-approximation architectures. In the broader signal-chain taxonomy, a pipelined ADC sits below sigma-delta ADCs (which dominate high-resolution low-bandwidth instrumentation) and above general-purpose SAR ADCs (which serve kilounit-per-second precision measurements). LTC2293CUP therefore occupies the communications-and-imaging niche where 12-bit resolution and 65 Msps are jointly required.
Key features include two simultaneously-sampling 12-bit ADC channels, an internal 2.5V reference that can be overdriven by an external reference via the SENSE pin, separate analog input (VA) and digital output (VD) supplies for noise isolation, and an exposed thermal pad that lowers junction-to-board thermal resistance. The differential input architecture supports single-ended or differential drive with input common-mode centered around 1.5V, simplifying interface to IF-stages, baseband filters, and CCD/CIS analog front-ends.
The LTC2293CUP supports high-impedance CMOS-compatible outputs and configurable full-scale range. The 64-lead QFN (9x9 mm) footprint matches the LTC2292/LTC2291 (40 Msps / 25 Msps) and is pin-compatible with the LTC2221 family, allowing system designers to scale sampling rate by simply substituting the ADC without re-laying-out the PCB.
Typical applications include cellular base-station receiver IF digitizers, ultrasound imaging arrays, cable-headend QAM/QPSK demodulators, CCD/CIS imaging pipelines, portable instrumentation, and multi-channel data-acquisition cards for industrial inspection. In each of these use cases, the LTC2293CUP's combination of dual channels, 12-bit resolution, and 65 Msps sample rate cuts board area, BOM cost, and software complexity versus two discrete single-channel ADCs.
When designing with the LTC2293CUP, separate analog and digital ground planes and stitch them only under the IC's exposed pad to prevent digital switching noise from coupling back into the analog input. Use short, matched-length differential traces from the input driver to keep aperture-delay mismatch below 0.3 LSB at full clock rate.
This page synthesizes distributor stock and pricing across DigiKey, Mouser, and Octopart, pin-compatible LTC2293/LTC2292/LTC2291 family drop-ins, and PCB-layout design notes that go beyond the manufacturer datasheet to help engineers shortlist a replacement or build a dual-channel 65 Msps acquisition front end on a 9x9 mm footprint.
直接替換替代品，適用於 LTC2293CUP — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2293CUP （相同外形與佔位） — 差異在於 Sample Rate, Input Type, Package, SFDR, SNR.
LTC2292CUP
✅ 直接替換聯絡詢價
查看資料表 →LTC2287CUP
✅ 直接替換聯絡詢價
查看資料表 →LTC2282CUP
✅ 直接替換聯絡詢價
查看資料表 →LTC2280CUP
✅ 直接替換聯絡詢價
查看資料表 →LTC2241IUP-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2221CUP
✅ 直接替換聯絡詢價
查看資料表 →LTC2293CUP 最大額定值與電氣特性
| Number of Channels | 2 |
| 解析度 | 12 bit |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| Input Type | Differential/Single-Ended |
| Analog Supply Voltage | 3 V (2.7 V to 3.3 V) |
| Digital Supply Voltage | 3 V (2.7 V to 3.3 V) |
| SNR | 71.3 dB at Nyquist |
| SFDR | 90 dB at Nyquist |
| Internal Reference | 2.5 V (SENSE pin selectable internal/external) |
| Input Common Mode | 1.5 V nominal |
| Full-Scale Input Range | 2 V pk-pk differential (with internal reference) |
| Output Format | CMOS, parallel |
| 封裝 | 64-QFN (9x9 mm) with exposed pad |
| 工作溫度 | 0C to +70C (commercial C suffix) |
| RoHS 狀態 | Compliant (PBF suffix) |
| Lead Finish | Au (lead-free) |
LTC2293CUP 腳位配置
| 腳位 1 | GND — Common ground |
| 腳位 2 | CLK — Clock input |
| 腳位 3 | CLKOUT — Clock output for synchronization |
| 腳位 4 | OF — Output overflow flag |
| 腳位 5 | SENSE — Reference sense / external reference input |
| 腳位 6 | VREF — Internal 2.5 V reference |
| 腳位 7 | REFCOMP — Reference compensation capacitor |
| 腳位 8 | OGND — Output driver ground |
| 腳位 9 | OVDD — Output driver supply (3 V) |
| 腳位 10 | DB0 — Data output bit 0 |
| 腳位 11 | DB1 — Data output bit 1 |
| 腳位 12 | DB2 — Data output bit 2 |
| 腳位 13 | DB3 — Data output bit 3 |
| 腳位 14 | DB4 — Data output bit 4 |
| 腳位 15 | DB5 — Data output bit 5 |
| 腳位 16 | DB6 — Data output bit 6 |
| 腳位 17 | DB7 — Data output bit 7 |
| 腳位 18 | DB8 — Data output bit 8 |
| 腳位 19 | DB9 — Data output bit 9 |
| 腳位 20 | DB10 — Data output bit 10 |
| 腳位 21 | DB11 — Data output bit 11 (MSB) |
| 腳位 22 | OGND — Output driver ground |
| 腳位 23 | OVDD — Output driver supply (3 V) |
| 腳位 24 | OGND — Output driver ground |
| 腳位 25 | DB0_B — Channel B data bit 0 |
| 腳位 26 | DB1_B — Channel B data bit 1 |
| 腳位 27 | DB2_B — Channel B data bit 2 |
| 腳位 28 | DB3_B — Channel B data bit 3 |
| 腳位 29 | DB4_B — Channel B data bit 4 |
| 腳位 30 | DB5_B — Channel B data bit 5 |
| 腳位 31 | DB6_B — Channel B data bit 6 |
| 腳位 32 | DB7_B — Channel B data bit 7 |
| 腳位 33 | DB8_B — Channel B data bit 8 |
| 腳位 34 | DB9_B — Channel B data bit 9 |
| 腳位 35 | DB10_B — Channel B data bit 10 |
| 腳位 36 | DB11_B — Channel B data bit 11 (MSB) |
| 腳位 37 | OF_B — Channel B overflow flag |
| 腳位 38 | OGND — Output driver ground |
| 腳位 39 | MODE — Output mode select |
| 腳位 40 | CS — Chip select / enable |
| 腳位 41 | VA — Analog supply (3 V) |
| 腳位 42 | AGND — Analog ground |
| 腳位 43 | VA — Analog supply (3 V) |
| 腳位 44 | INA+ — Channel A positive analog input |
| 腳位 45 | INA- — Channel A negative analog input |
| 腳位 46 | AGND — Analog ground |
| 腳位 47 | VA — Analog supply (3 V) |
| 腳位 48 | REFCOMP_B — Channel B reference compensation |
| 腳位 49 | SENSE_B — Channel B reference sense |
| 腳位 50 | VREF_B — Channel B internal reference |
| 腳位 51 | VA — Analog supply (3 V) |
| 腳位 52 | AGND — Analog ground |
| 腳位 53 | INB- — Channel B negative analog input |
| 腳位 54 | INB+ — Channel B positive analog input |
| 腳位 55 | VA — Analog supply (3 V) |
| 腳位 56 | AGND — Analog ground |
| 腳位 57 | VA — Analog supply (3 V) |
| 腳位 58 | VD — Digital supply (3 V) |
| 腳位 59 | DGND — Digital ground |
| 腳位 60 | VD — Digital supply (3 V) |
| 腳位 61 | VD — Digital supply (3 V) |
| 腳位 62 | DGND — Digital ground |
| 腳位 63 | NC — Not connected |
| 腳位 64 | NC — Not connected |
典型應用
LTC2293CUP 適用於 6 應用s: Cellular Base Station IF Digitizer, Ultrasound Imaging Array Receiver, Cable Headend QAM/QPSK Demodulator, Multi-Channel Data Acquisition Card, CCD/CIS Imaging Pipeline, Portable Instrumentation and Test Equipment.
Cellular Base Station IF Digitizer
The LTC2293CUP's dual 12-bit 65 Msps channels and 71.3 dB SNR suit dual-path IF digitization in WCDMA/LTE base-station receivers, where two matched ADCs sample I and Q (or two diversity branches) simultaneously. Its 90 dB SFDR preserves linearity across the cellular band even at full-scale input. The 64-QFN footprint and 3V supply keep the front end compact and efficient on the receive card, while separate VA/VD pins minimize digital-noise coupling into the analog input.
推薦
Ultrasound Imaging Array Receiver
Phased-array ultrasound receivers need matched simultaneous sampling across many channels, and the LTC2293CUP delivers dual 65 Msps channels per chip with low aperture-delay mismatch. Its 12-bit resolution and 71.3 dB SNR keep B-mode dynamic range usable down to small-amplitude echoes, while the 9x9 mm QFN footprint allows dense multi-channel boards. Lowering the channel count per ADC simplifies beamformer FPGA/ASIC fan-in versus single-channel ADC arrays.
推薦
Cable Headend QAM/QPSK Demodulator
Cable modem termination systems (CMTS) and edge QAM modulators digitize dense constellations across hundreds of MHz, and the LTC2293CUP's 65 Msps per channel captures two carriers per chip. With 90 dB SFDR at Nyquist it preserves QAM-256/1024 error-vector magnitude, while 71.3 dB SNR supports high-order modulation error floors. The 3V single-supply operation and exposed-pad QFN help the head-end chassis meet thermal and power budgets.
推薦
Multi-Channel Data Acquisition Card
Industrial inspection and scientific instruments frequently require 8 to 32 simultaneously-sampled channels at 12-bit resolution, and stacking LTC2293CUP chips delivers 2 channels per IC with matched timing. The dual-channel integration halves board area vs single-channel ADCs and reduces FPGA/serializer pin count. The CMOS parallel output is compatible with low-cost FPGAs used in industrial DAQ platforms.
推薦
CCD/CIS Imaging Pipeline
High-end digital still cameras and document scanners route analog CCD/CIS outputs through dual-channel 12-bit ADCs at video rates. The LTC2293CUP digitizes the two color channels in parallel at 65 Msps, avoiding interleaving artifacts. Its differential inputs accept direct coupling from correlated double-sampling (CDS) stages, and the internal 2.5V reference simplifies the analog front end. Lower-power 3V operation extends battery life in portable imaging rigs.
推薦
Portable Instrumentation and Test Equipment
Handheld oscilloscopes, spectrum analyzers, and bench-top digitizers benefit from the LTC2293CUP's dual 65 Msps channels in a 9x9 mm footprint, supporting two input channels per ADC IC. The 71.3 dB SNR floor and 90 dB SFDR deliver clean FFT bins for sub-Nyquist signal analysis. Single 3V supply and exposed-pad QFN simplify battery-powered and thermally-constrained designs where PCB real estate is at a premium.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2293CUP — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2292CUP | LTC2287CUP | LTC2282CUP | LTC2280CUP | LTC2221CUP |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 | 1 | 1 |
| Resolution | 12 bit | 12 bit | 10 bit | 12 bit | 10 bit | 12 bit |
| Sample Rate | 65 Msps | 40 Msps | 40 Msps | 105 Msps | 105 Msps | 65 Msps |
| Supply Voltage | 3 V | 3 V | 3 V | 3 V | 3 V | 3 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Output Format | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel |
主要差異化特點
- Dual simultaneous-sampling 12-bit channels at 65 Msps in one QFN (對比LTC2282CUP)
- Higher SNR and SFDR vs 10-bit family (對比LTC2287CUP)
- Pin-compatible with lower-speed family siblings (對比LTC2292CUP / LTC2291)
設計說明
Use separate analog (VA), digital (VD), and output-driver (OVDD) planes, stitching the analog and digital grounds only under the IC's exposed pad to avoid digital switching noise coupling back into the analog input. Place 0.1 uF ceramic bypass caps within 3 mm of each VA/VD/OVDD pin, and a 10 uF tantalum or ceramic bulk cap near the IC for high-frequency energy storage. Keep CLK traces short and use a series damping resistor if the source driver impedance is below 20 ohms to control aperture-jitter sensitivity.
Drive the analog inputs differentially using a wideband ADC driver (e.g. AD8138) and route traces as tightly coupled 100-ohm differential pairs on the top layer over a continuous ground plane. Length-match the INA+ / INA- and INB+ / INB- pairs to within 0.5 mm to keep aperture-delay mismatch below 0.3 LSB at 65 Msps. Maintain constant 50-ohm characteristic impedance on the CLK input and route away from the analog inputs to avoid coupling.
Solder the exposed pad to a copper pour with at least 12 thermal vias to the inner ground plane. At 65 Msps dual-channel operation with 3 V supply, the device dissipates roughly 250 mW; without the exposed pad soldered, junction temperature can exceed 100 C in still air. Use multi-layer PCB with thermal vias for production designs.
Do not float the SENSE pin - tie it to VREF for internal reference mode or to VA for external reference mode before power-up. Do not drive SENSE with a low-impedance logic device; per datasheet 229321fa, use a resistor divider close to the pin. Avoid using CLKOUT to drive additional ADCs when tight aperture matching is required; instead use an external low-jitter clock fan-out buffer.
合規資訊
RoHS compliance confirmed by PBF suffix on datasheet title. AEC-Q100 not applicable (commercial-grade part); the I-suffix variant LTC2293IUP covers industrial temperature range.
