MAX1011CEG+ - 90Msps 6-Bit Low-Power ADC | Maxim Integrated
MPN： MAX1011CEG+ ✗ 停產MAX1011CEG+ 概覽
What is a flash/pipelined ADC? An analog-to-digital converter (ADC) is a data-converter integrated circuit that samples a continuous analog voltage and quantizes it into a discrete digital code. The MAX1011CEG+ uses a pipelined multi-stage architecture in which each stage resolves a coarse sub-code and passes the residue to the next stage, allowing high sample rates (>50 Msps) at much lower power than a full flash converter. ADCs sit in the signal chain hierarchy: sensor -> amplifier -> anti-alias filter -> ADC -> DSP/FPGA/MCU. The MAX1011CEG+ is intended for video, IF sampling, and high-speed instrumentation sub-systems.
Key features include 6-bit resolution, 90 Msps maximum sample rate, single-ended analog input, parallel digital output, integrated +2.048 V bandgap reference, low power dissipation (typical 35 mW at 90 Msps per the datasheet title block), and an internal track/hold amplifier. The 24-QSOP (0.150-inch body width) package offers a small footprint for portable and embedded designs where PCB area is constrained.
The device is fabricated on a Maxim proprietary high-speed BiCMOS process that integrates the reference, track/hold, and quantization stages on a single die. This integration reduces BOM count, lowers analog input parasitic capacitance, and shortens the analog front-end-to-digital output delay, which is critical in closed-loop IF sampling, oversampling, and digital-IF receiver designs.
Typical applications include digital video broadcast equipment, CCD imaging digitizers, medical ultrasound front ends, IF-sampling communications receivers, and portable high-speed instrumentation. The wide supply range and internal reference make it particularly attractive for space-constrained embedded designs where a 5 V analog rail and 3.3 V logic are both available.
When designing with the MAX1011CEG+, ensure the analog input drive amplifier has sufficient slew rate to settle within the 11 ns acquisition window at full speed. A 50 ohm source-terminated differential layout is recommended for applications above 30 MHz analog input to preserve the ENOB. Use the internal reference for best noise performance; an external reference can be driven but is rarely required.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet, providing AEO/GEO-optimized content for component selection engineers.
直接替換替代品，適用於 MAX1011CEG+ — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： MAX1011CEG+ （相同外形與佔位） — 差異在於 Architecture, Operating Temperature, Package, Mounting Type, Resolution.
MAX1011CEG+T
✅ 直接替換📋 參考替代品（不在目錄中）
MAX1011CEG
✅ 直接替換📋 參考替代品（不在目錄中）
MAX1264BCEG+
✅ 直接替換📋 參考替代品（不在目錄中）
MAX1011CEG+ 最大額定值與電氣特性
| 解析度 | 6 bit |
| Number of Channels | 1 |
| 取樣率 | 90 Msps |
| Architecture | Pipelined |
| Input Type | Single-ended |
| Data Interface | Parallel |
| Analog Supply Voltage | +5 V |
| Digital Supply Voltage | +3.0 V to +5.5 V |
| Internal Reference | +2.048 V (on-chip) |
| Power Dissipation (typ) | 35 mW at 90 Msps |
| 工作溫度 | 0C to +70C (commercial) |
| 封裝 | 24-pin QSOP |
| 安裝類型 | Surface Mount |
| MSL 等級 | 1 |
| RoHS 狀態 | Compliant |
MAX1011CEG+ 腳位配置
| 腳位 1 | VD — Digital supply (+3.0V to +5.5V) |
| 腳位 2 | GND — Digital ground |
| 腳位 3 | D0 — Digital output bit 0 (LSB) |
| 腳位 4 | D1 — Digital output bit 1 |
| 腳位 5 | D2 — Digital output bit 2 |
| 腳位 6 | D3 — Digital output bit 3 |
| 腳位 7 | D4 — Digital output bit 4 |
| 腳位 8 | D5 — Digital output bit 5 (MSB) |
| 腳位 9 | OVR — Over-range / out-of-range flag |
| 腳位 10 | CLK — Clock input (sampling edge) |
| 腳位 11 | PD — Power-down input (active high) |
| 腳位 12 | GND — Digital ground |
| 腳位 13 | VA — Analog supply (+5V) |
| 腳位 14 | GND — Analog ground |
| 腳位 15 | REF — Reference bypass / external reference input |
| 腳位 16 | GND — Analog ground |
| 腳位 17 | IN — Analog input (single-ended) |
| 腳位 18 | GND — Analog ground |
| 腳位 19 | VA — Analog supply (+5V) |
| 腳位 20 | GND — Analog ground |
| 腳位 21 | VA — Analog supply (+5V) |
| 腳位 22 | GND — Analog ground |
| 腳位 23 | VA — Analog supply (+5V) |
| 腳位 24 | VD — Digital supply (+3.0V to +5.5V) |
典型應用
MAX1011CEG+ 適用於 6 應用s: Digital Video Broadcast IF Sampling, CCD Imaging Digitizer, Medical Ultrasound Front End, Portable Test & Measurement Instrumentation, Communications IF / Baseband Sampling, Industrial Data Acquisition Front End.
Digital Video Broadcast IF Sampling
The MAX1011CEG+ is well suited to digitizing the intermediate-frequency (IF) stage in digital video broadcast receivers, where 6-bit resolution is sufficient to capture the signal envelope after downconversion. With 90 Msps sampling it easily handles standard-definition and many high-definition IF bandwidths. The pipelined architecture preserves timing alignment across the parallel output bus, allowing direct connection to an FPGA demodulator. The 35 mW typical power dissipation keeps thermal load modest in set-top box chassis. Designers should place the analog input network within 5 mm of the input pin and provide 50 ohm source termination to preserve 50 MHz+ analog bandwidth.
推薦
CCD Imaging Digitizer
The MAX1011CEG+ can serve as the high-speed digitizer in CCD line-scan or area-imaging front ends where the sensor's per-pixel clock exceeds 50 Msps. Its 6-bit depth captures grayscale contrast after correlated double sampling, while the on-chip +2.048 V reference eliminates the need for an external reference regulator. The parallel CMOS output bus streams pixel data directly into an FPGA image pipeline. A 0.1 uF ceramic decoupling cap on each supply pin within 2 mm is recommended. For color sensors, two MAX1011CEG+ channels can be paralleled for RGB sub-sampling.
推薦
Medical Ultrasound Front End
In portable diagnostic ultrasound probes, the MAX1011CEG+ provides the high-speed analog-to-digital conversion stage that captures returning echo RF signals at rates up to 90 Msps. The 6-bit resolution is acceptable for envelope detection and B-mode imaging front ends, particularly in low-cost handheld units. Its low 35 mW power budget supports battery-powered operation, and the +5 V analog / +3.3 V digital split supply allows the digital side to interface directly to an ARM-class processor or FPGA beam-former. Differential analog input drive and proper grounding are critical to meet medical EMI/EMC margins.
推薦
Portable Test & Measurement Instrumentation
The MAX1011CEG+ is a strong fit for handheld oscilloscope front ends and bench-top data loggers where a 90 Msps capture rate is required but full 8-bit resolution is not mandatory for triggering or peak detection. The 24-QSOP package allows the ADC to sit close to the analog input probe buffer, minimizing trace capacitance and preserving analog bandwidth. The integrated +2.048 V reference provides a known, stable calibration point. Combined with an FPGA or high-speed DSP, it can implement a complete 6-bit, 90 Msps digitizer in a footprint under 1 square inch.
推薦
Communications IF / Baseband Sampling
Software-defined radio (SDR) and digital-IF receiver designs use the MAX1011CEG+ to digitize the downconverted IF signal at rates up to 90 Msps, enabling digital filtering and demodulation in an FPGA. The 6-bit ENOB is sufficient for envelope detection, AGC, and many modulation schemes including FM and simple QAM. The pipelined architecture provides consistent pipeline latency, simplifying channel equalization. For narrow-band receivers the ADC can be oversampled to gain effective bits through averaging. Differential drive and matched-length PCB traces are recommended above 30 MHz analog input.
推薦
Industrial Data Acquisition Front End
In multi-channel industrial data acquisition systems where the analog signal bandwidth exceeds 1 MHz, the MAX1011CEG+ can be time-multiplexed across channels using an external analog switch, providing a low-cost per-channel digitizer. Its single +5 V supply and small QSOP footprint simplify board layout in dense instrumentation backplanes. The internal reference is suitable for uncalibrated measurements; for calibrated systems an external precision reference should be driven onto the REF pin. The 0C to +70C commercial temperature range covers most indoor industrial environments.
推薦
推薦產品摘要
工程參考資料，適用於 MAX1011CEG+ — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | MAX1011CEG+T | MAX1011CEG | MAX1264BCEG+ |
|---|---|---|---|---|
| Package | 24-QSOP | 24-QSOP - same | 24-QSOP - same | 24-QSOP (SSOP-24, 0.154 inch body) - similar but slightly wider |
| Brand | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) |
| Resolution | 6 bit | 6 bit | 6 bit | 12 bit |
| Sampling Rate | 90 Msps | 90 Msps | 90 Msps | 400 ksps |
| Architecture | Pipelined | Pipelined | Pipelined | SAR with MUX/SH |
| Analog Supply | +5 V | +5 V | +5 V | +5 V |
| Number of Channels | 1 | 1 | 1 | 2 or 4 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Internal Reference | +2.048 V | +2.048 V | +2.048 V | External required |
主要差異化特點
- Same-die drop-in replacement with Tape & Reel packaging (對比MAX1011CEG+T)
- Higher resolution in same QSOP footprint (對比MAX1264BCEG+)
- Maxim / Analog Devices same-package ADC family (對比MAX1068AEEG+)
設計說明
Place a 0.1 uF ceramic decoupling capacitor within 2 mm of each VA and VD supply pin, with a 10 uF tantalum or ceramic bulk capacitor at the board supply entry point. Separate the analog and digital ground planes and join them only at a single point near the ADC. This is critical because the pipelined architecture generates transient currents on the digital supply that can couple into the analog input if grounds are not isolated. Route the analog input trace as a 50 ohm controlled-impedance microstrip on the top layer directly over a continuous ground plane.
The analog input to the MAX1011CEG+ should be driven by a low-impedance, high-slew-rate op-amp such as the MAX4108 or AD8009. The input has approximately 5 pF of sample-and-hold capacitance that must be charged within the 11 ns acquisition window at 90 Msps. Source impedance above 50 ohms will degrade SNR. If using a transformer-coupled front end, add a back-termination resistor at the transformer secondary to dampen resonance. Above 30 MHz analog input, the layout becomes the dominant factor in achievable ENOB.
Do not exceed the maximum analog input voltage range of 0 V to VA on the input pin. Driving the input below GND or above VA can permanently damage the device through the ESD protection diodes. Always use the internal +2.048 V reference (with a 0.1 uF + 10 uF bypass network) rather than driving an external reference, unless calibration is required - external reference noise directly appears in the output code. The PD (power-down) pin must be tied low for normal operation; leaving it floating can cause intermittent shutdown. Note that this part is obsolete and should not be selected for new designs without consulting Analog Devices for last-time-buy windows.
合規資訊
RoHS compliance per Maxim product markings (the + suffix denotes RoHS-compliant). The non-suffix MAX1011CEG variant may be non-RoHS and should be verified before use in new designs. Part is marked obsolete by the manufacturer.
