MAX120EWG+ - 12-Bit 500ksps SAR ADC | Maxim Integrated
MPN： MAX120EWG+ ✓ 啟用中MAX120EWG+ 概覽
An ADC converts an analog input voltage into a digital code for processing by a microcontroller, DSP, FPGA, or other digital controller. The MAX120EWG+ belongs to the ADC hierarchy and specifically implements a successive-approximation architecture, commonly abbreviated SAR. Its 12-bit resolution provides 4,096 digital code levels, while the integrated track-and-hold function supports acquisition of rapidly changing input signals at rates up to 500ksps.
The verified manufacturer and distributor information identifies the device as a one-input, 12-bit SAR ADC with a 500ksps sampling rate. It also identifies the MAX120 family as ADCs with track/hold and reference functions. These characteristics make the converter appropriate for industrial monitoring, industrial instrumentation, and embedded data-acquisition systems where a compact surface-mount ADC is needed.
The MAX120EWG+ uses a parallel data interface rather than a serial SPI or I2C interface. Parallel output transfers the newly converted code directly to digital logic, which can simplify connections to older processor buses and FPGA input registers. Because the device is a successive-approximation converter, designers should account for acquisition and conversion time when defining the sampling interval and should preserve the analog input signal during the specified track-and-hold interval.
Typical uses include digitizing process-control inputs, capturing sensor outputs, sampling waveforms in industrial test equipment, and providing front-end conversion for embedded control systems. The 24-SOIC package also allows reuse of board layouts designed around other qualified 24-pin SOIC converters when pin functions, supply requirements, and acquisition behavior have been verified against the datasheet.
The primary design consideration is signal conditioning. The ADC input must remain within the valid analog input range, reference behavior must meet the required accuracy, and the source impedance must permit the internal track-and-hold capacitor to acquire the required voltage during each sampling period. Designers should also place input and reference decoupling close to the device and maintain a quiet return path from the analog input to the device ground.
This product page combines the verified MAX120EWG+ specifications, distributor sourcing information, package details, and directly supported replacement references with practical selection guidance. It is designed to help engineers evaluate the converter without confusing it with lower-resolution, slower, or electrically incompatible ADC alternatives.
直接替換替代品，適用於 MAX120EWG+ — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： MAX120EWG+ （相同外形與佔位） — 差異在於 Conversion Architecture, Package, Sampling Rate.
MAX120EWG
✅ 直接替換📋 參考替代品（不在目錄中）
MAX120CWG+T
✅ 直接替換📋 參考替代品（不在目錄中）
MAX120EWG+ 最大額定值與電氣特性
| 解析度 | 12 bit |
| 取樣率 | 500ksps |
| Conversion Architecture | Successive Approximation (SAR) |
| Number of Inputs | 1 |
| Input Type | Single-ended |
| Data Interface | Parallel |
| Track and Hold | Integrated |
| Reference | Internal reference |
| Digital Supply Voltage | 5 V |
| Analog Supply Voltage Range | -10.8 V to 15.75 V |
| 封裝 | 24-SOIC |
| Package Code | SOP |
| Package Shape | Rectangular |
| Terminal Form | Gull wing |
| Number of Terminals | 24 |
| 安裝類型 | Surface mount |
| Temperature Grade | Industrial |
MAX120EWG+ rectangular 腳位配置指南
MAX120EWG+（rectangular 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： MAX120EWG+.
請參閱 資料表 以查看完整腳位配置。
典型應用
MAX120EWG+ 適用於 6 應用s: Industrial Process Monitoring, Data-Acquisition Instrumentation, Embedded Sensor Interface, FPGA-Based Signal Acquisition, Control-System Analog Front End, Test and Measurement Signal Capture.
Industrial Process Monitoring
The MAX120EWG+ fits process-monitoring systems that digitize pressure, temperature, position, or level signals and require a 500ksps sampling capability. Its 12-bit SAR conversion provides 4,096 code levels for representing an analog measurement, while the single-ended input simplifies channel selection around a multiplexer. The 24-SOIC package supports compact board construction, and the parallel interface can feed a processor or FPGA directly. A practical design should buffer high-impedance sensors, limit the analog input to the datasheet range, and use local decoupling to keep the reference and converter supply stable.
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Data-Acquisition Instrumentation
The MAX120EWG+ is appropriate for compact data-acquisition instrumentation that samples an analog waveform and transfers each 12-bit result to digital control logic. A conversion rate of up to 500ksps provides sufficient timing margin for capturing moderately fast signals, and the integrated track/hold function separates acquisition from conversion. The parallel data interface avoids serial-bus overhead when the converter is connected directly to an FPGA register or embedded processor bus. Signal conditioning, sampling bandwidth, settling behavior, and input-source impedance must be verified before selecting acquisition timing.
推薦
Embedded Sensor Interface
The MAX120EWG+ can serve as the analog front end for embedded sensors whose outputs must be digitized before control decisions are made. Its 12-bit resolution provides a practical balance between conversion rate and code density, while the single-ended input can be paired with a sensor amplifier or multiplexer. The 500ksps capability permits rapid sampling when the application includes oversampling or multiple sequential measurements. Engineers should ensure the selected sensor can charge the track-and-hold capacitor during the available acquisition interval and should keep high-current digital return paths away from the analog input.
推薦
FPGA-Based Signal Acquisition
The MAX120EWG+ is well suited to FPGA-based acquisition because it combines a 500ksps SAR conversion rate with a 12-bit parallel output. The digital code can be captured in input registers without adding a serial protocol, and the SOIC package can be placed close to the converter pins to limit board-trace effects. The design must still observe acquisition and conversion timing, establish a clean reference, and account for parallel-bus skew if multiple output lines change near the sampling boundary. FPGA I/O voltage compatibility must be checked against the converter's verified 5 V digital supply requirement.
推薦
Control-System Analog Front End
The MAX120EWG+ can be used as the conversion stage in a feedback-control system that measures an analog command or condition and supplies a digital value to a controller. Its 12-bit resolution offers 4,096 available codes, while the 500ksps rating leaves substantial throughput relative to many slow feedback loops. The parallel output can be sampled directly by embedded logic, and the integrated track/hold supports repeatable acquisition when driven by a suitable source. For reliable operation, the analog signal must remain within the input limits, and the controller must account for the conversion pipeline in its timing.
推薦
Test and Measurement Signal Capture
The MAX120EWG+ can support test and measurement modules that digitize a conditioned analog output for display, logging, or automated evaluation. Its 500ksps maximum rate is suitable for many general-purpose instrumentation channels, while 12-bit resolution provides useful measurement granularity without requiring a more complex converter. The parallel interface can simplify connection to acquisition logic, and the 24-SOIC package is compatible with compact instrument boards. Designers should characterize input bandwidth, acquisition settling, reference accuracy, and code noise at the intended signal levels before using the results for precision measurements.
推薦
推薦產品摘要
工程參考資料，適用於 MAX120EWG+ — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | MAX120EWG | MAX120CWG+T |
|---|---|---|---|
| Package | 24-SOIC | 24-SOIC | 24-SOIC |
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated |
| Resolution | 12 bit | 12 bit | 12 bit |
| Conversion Architecture | Successive Approximation (SAR) | Successive Approximation (SAR) | SAR |
主要差異化特點
- Directly documented same-package replacement path (對比MAX120EWG)
- Exact + suffix sourcing (對比MAX120CWG+T)
- Parallel acquisition architecture (對比MAX120EWG)
設計說明
Do not treat the 500ksps figure as permission to use an arbitrary source impedance or acquisition interval. The internal track-and-hold network must charge to the required accuracy before conversion. Verify the input-source impedance, external buffer settling time, and acquisition timing in the manufacturer datasheet. If those details are unavailable, use an appropriately buffered input and validate acquisition settling at the intended signal frequency.
Place the converter close to the analog source and route the input as a short, guarded trace away from switching nodes. Keep the digital output and supply-return paths separate from the input and reference routing. Provide local supply and reference decoupling according to the manufacturer layout guidance, and use a continuous ground reference beneath the analog section where the board construction permits.
The parallel output can create simultaneous fast-edge current on multiple data lines. Route the 12-bit bus with short traces and matched topology to the receiving logic, and avoid splitting the bus across distant connectors or ground-plane boundaries. Confirm that the connected digital device accepts the converter's 5 V digital interface and verify bus timing against the receiver's setup and hold requirements.
Separate analog and digital supply-return paths where the circuit design permits, and keep converter return current out of sensitive signal paths. Because the verified listing identifies a 5 V digital supply and a -10.8 V to 15.75 V analog supply range, the actual rail arrangement must be selected from the datasheet. Confirm sequencing, allowable combinations, and decoupling values before power-up rather than inferring them from the category description.
合規資訊
The verified web excerpts do not state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status. Compliance must be confirmed from the current manufacturer product documentation or declaration of conformity.
