PCA9517DG4 - 2-Channel 400kHz I2C Level Translator | Texas Instruments
MPN： PCA9517DG4 ✓ 啟用中PCA9517DG4 概覽
An I2C level translator, also called a voltage-level translator, is an interface IC placed between two bidirectional open-drain buses. The PCA9517 belongs to the I2C buffer/repeater hierarchy, where it combines bidirectional buffering, voltage-level translation, and bus-segmentation functions. Its two-channel architecture allows SDA and SCL to cross independently between a low-voltage domain and a higher-voltage domain while preserving I2C clock stretching and SMBus-compatible operation.
Key features include two bidirectional channels, operation from 0.9 V on the low side to 5.5 V on the high side, a maximum I2C bus speed of 400 kHz, and compatibility with both I2C and SMBus systems. The buffered channels can extend usable bus reach by isolating capacitance accumulated on the source side from the destination side. A quoted propagation delay of 170 ns and input capacitance of 6 pF are important when selecting pull-up resistors and evaluating timing margins.
The PCA9517 uses bidirectional buffers rather than unidirectional voltage-level shifters. Because I2C and SMBus signals are open-drain and pulled up externally, each translated channel can conduct in either direction. This makes the device suitable for a host controller operating at a lower voltage communicating with sensors, memory devices, or expansion components whose pull-up network uses a higher supply voltage. The manufacturer describes the PCA9517 as a CMOS and BiCMOS integrated circuit for these applications.
Typical uses include voltage adaptation between 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains; isolating a long or heavily loaded I2C branch; and extending communication between a microcontroller and higher-voltage sensors or EEPROMs. Because both SDA and SCL require translation, the complete two-channel arrangement keeps data and clock voltage domains aligned.
Designers must provide correct pull-up resistors on each side of the translator and account for the 170 ns propagation delay when calculating the maximum operating frequency. The 8-SOIC package is also used by the PCA9515A, while Texas Instruments' TCA9517 is identified as a comparable dual bidirectional I2C buffer. Review device-specific enable behavior, bus capacitance, and logic thresholds before finalizing a replacement.
This page organizes the PCA9517DG4 specifications, replacement candidates, application guidance, and design considerations into one engineering-focused reference. It also distinguishes the published 0.9 V low-side capability from the 2.7 V to 5.5 V high-side range and identifies package and functional differences that matter when reusing an existing PCB.
直接替換替代品，適用於 PCA9517DG4 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： PCA9517DG4 （相同外形與佔位） — 差異在於 Package, Function, Number of Channels, RoHS Status.
TCA9517DR
✅ 直接替換聯絡詢價
查看資料表 →PCA9515ADR
✅ 直接替換聯絡詢價
查看資料表 →PCA9517DG4 規格
| Channel Count | 2 channels |
| Bus Compatibility | I2C bus and SMBus |
| Maximum I2C Bus Frequency | 400 kHz |
| Low-Side Minimum Supply Voltage | 0.9 V |
| High-Side Supply Voltage Range | 2.7 V to 5.5 V |
| Overall Supply Voltage Range | 2.7 V to 5.5 V |
| Buffer Direction | Bidirectional |
| Delay Time | 170 ns |
| 輸入電容 | 6 pF |
| 供應電流 | 5 mA |
| Device Type | Level-translating I2C bus repeater |
| Logic Type | I2C logic |
| Integrated Circuit Technology | CMOS and BiCMOS |
| 封裝 | 8-SOIC (0.154 inch, 3.90 mm width) |
| 安裝類型 | Surface mount |
PCA9517DG4 8-soic (0.154 inch, 3.90 mm width) 腳位配置指南
PCA9517DG4（8-soic (0.154 inch, 3.90 mm width) 封裝）的腳位配置。 腳位編號、功能與連接圖定義於製造商資料手冊中。請參閱該手冊以取得確切的封裝尺寸與焊接指引。
無詳細腳位定義資料： PCA9517DG4.
請參閱 資料表 以查看完整腳位配置。
典型應用
PCA9517DG4 適用於 6 應用s: Low-Voltage Controller to 5 V Peripheral Bus, I2C Bus Extension, SMBus Voltage Adaptation, Mixed-Voltage Sensor Interface, EEPROM and Memory Bus Isolation, Multi-Domain Control Module.
Low-Voltage Controller to 5 V Peripheral Bus
The PCA9517DG4 fits between a low-voltage controller and a 3.3 V or 5 V I2C peripheral bus when the two sides cannot share one pull-up voltage. Its low-side operation extends down to 0.9 V, while the high side accepts 2.7 V to 5.5 V, allowing SDA and SCL to cross voltage domains without unidirectional level shifters. The two bidirectional channels preserve clock stretching and SMBus-compatible behavior. Keep pull-up networks separate on each side, account for the quoted 170 ns delay, and verify the attached peripheral's absolute voltage limits.
推薦
I2C Bus Extension
Use the PCA9517DG4 as a repeatable boundary on an I2C segment whose accumulated capacitance would otherwise burden the controller or remote devices. Its bidirectional SDA and SCL buffers separate the source and destination bus sections, while the 400-kHz operating capability supports Fast-mode I2C communication. The quoted 6 pF input capacitance must be included when sizing pull-up resistors and estimating loading. Separate external pull-ups should establish valid logic levels in each voltage domain, and system timing must include the 170 ns propagation delay.
推薦
SMBus Voltage Adaptation
The PCA9517DG4 is appropriate for SMBus-compatible systems where a manager operates at one logic voltage and slave devices use another. Because the PCA9517 is an I2C/SMBus level-translating repeater, both SDA and SCL can be translated bidirectionally while retaining clock stretching. The 400-kHz limit defines the highest supported bus rate, and the 0.9 V low-side capability provides additional headroom for low-voltage managers. Confirm each side's pull-up voltage and the slave's allowable input range before deployment.
推薦
Mixed-Voltage Sensor Interface
The PCA9517DG4 can connect a low-voltage embedded controller to sensors, converters, or other instrumentation using a higher I2C pull-up voltage. Translating SDA and SCL together prevents the clock from remaining at one logic level while data crosses into another. Its 2.7 V to 5.5 V high-side range supports common 3.3 V and 5 V buses, while the low side can extend down to 0.9 V. Review sensor power sequencing, bus capacitance, and the translator's 170 ns delay when the sensor also imposes a clock-stretching limit.
推薦
EEPROM and Memory Bus Isolation
Placing the PCA9517DG4 between a controller and an I2C EEPROM or memory device can isolate the memory bus from capacitance on the controller-side segment. The buffered SDA and SCL paths maintain bidirectional communication, while separate pull-up networks let the EEPROM operate from 3.3 V or 5 V even when the controller uses a lower voltage. The device's 400-kHz capability covers common memory interfaces, but address setup, hold, and access timing still depend on the memory device. Validate timing with the 170 ns translator delay included.
推薦
Multi-Domain Control Module
The PCA9517DG4 is useful in a control module that combines a low-voltage processor rail with higher-voltage communications or expansion logic. Its two independent bidirectional channels translate both I2C clock and data, allowing the higher-voltage section to retain a conventional pull-up arrangement. This arrangement reduces the need for a processor pin to tolerate a higher bus voltage. Designers should confirm enable or power-sequencing requirements, use the manufacturer application circuit as a starting point, and preserve adequate timing margin around the 400-kHz operating ceiling.
推薦
推薦產品摘要
工程參考資料，適用於 PCA9517DG4 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | TCA9517DR | PCA9515ADR |
|---|---|---|---|
| Package | 8-SOIC (0.154 inch, 3.90 mm width) | 8-SOIC | 8-SOIC |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Channel Count | 2 channels | 2 channels | 2 channels |
| Buffer Direction | Bidirectional | Bidirectional | Bidirectional |
| Bus Compatibility | I2C bus and SMBus | I2C bus | I2C bus |
主要差異化特點
- Lower low-side operating capability (對比TCA9517DR)
- Two complete bidirectional I2C channels (對比TCA9517DR)
- SMBus-compatible level translation (對比PCA9515ADR)
- SOIC footprint reuse (對比PCA9515ADR)
設計說明
Use separate pull-up networks for SDA and SCL on each side of the translator. Connecting both voltage domains to one pull-up supply defeats the level-shifting function and can expose the low-voltage devices to excessive voltage. Select resistor values from the capacitance of each isolated bus section and the required rise time. Because the PCA9517DG4 uses open-drain-compatible bidirectional buffering, each side must retain a valid passive pull-up.
Include the quoted 170 ns propagation delay when evaluating SCL timing, especially at the 400-kHz maximum rate. Calculate worst-case rise time from each bus section's total capacitance and pull-up resistance, and check clock-stretching behavior separately because the remote device may hold SCL low. Treat the translator as two independently loaded channels rather than assuming the source-side capacitance is completely hidden from the destination.
Place the PCA9517DG4 close to the boundary between low-voltage and high-voltage bus sections. Keep SDA and SCL routing lengths and topology similar to minimize propagation-time and capacitance differences between the two translated channels. Provide a solid ground reference, avoid long stubs into unused connectors, and place pull-up resistors near the devices that establish each domain's logic level. Follow the manufacturer recommended application circuit when reproducing the 8-SOIC footprint.
Confirm that both voltage domains can be powered in the sequence required by the attached controller and peripherals. The PCA9517DG4 supports low-side voltages down to 0.9 V and high-side voltages from 2.7 V to 5.5 V, but power-ramp behavior can affect bus logic if either side becomes active before its pull-up network is valid. Use the device enable or power-sequencing arrangement specified by the manufacturer for the selected system configuration.
合規資訊
The verified product and distributor listings do not explicitly state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status.