PIC18C601-I/PT - 8-bit 25MHz ROMless MCU 64-TQFP | Microchip
MPN： PIC18C601-I/PT ✗ 停產PIC18C601-I/PT 概覽
An 8-bit ROMless microcontroller is a CPU core that requires program code to be stored in an external memory device (EPROM, Flash, or SRAM) rather than internal non-volatile memory. In the broader system hierarchy it sits as an MCU (microcontroller) -> embedded processor -> integrated circuit, and is commonly selected for designs that need larger or more flexible program storage than on-chip flash parts can provide.
Key features include a C-optimized RISC instruction set with only 77 single-word instructions, linear program memory addressing to 2 Mbytes, an external memory interface supporting both 16-bit and 8-bit bus widths, and a programmable oscillator range supporting external clock sources up to 40 MHz. The device also integrates a wide operating voltage range of 4.2V to 5.5V and an industrial temperature grade of -40C to +85C.
Architecturally, the PIC18C601 uses a 16-bit instruction word with an 8-bit data path, a hardware multiplier, and a 31-level deep stack suitable for high-level language compilers. The external memory bus is configurable for separate address/data lines or multiplexed modes, making it adaptable to legacy external EPROM and modern parallel Flash parts. The lack of on-chip program memory reduces unit cost for high-volume applications and supports field-upgradable firmware via external memory swap.
Typical applications include industrial control systems, automotive body electronics, point-of-sale terminals, and consumer appliances requiring external program memory. The wide external memory bus is also suited for legacy designs migrating from PIC16C5X/PIC12CXXX devices. The I suffix indicates the industrial temperature grade (-40C to +85C), and the PT suffix denotes the 64-pin TQFP surface-mount package.
When designing with this part, allocate a minimum of 5 ns external memory access timing budget and place decoupling capacitors (100 nF ceramic plus 10 uF bulk) within 25 mm of the VDD pins. Designers should also confirm that external memory devices meet the 25 MHz (40 ns) cycle time at the chosen VDD level.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替換替代品，適用於 PIC18C601-I/PT — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： PIC18C601-I/PT （相同外形與佔位） — 差異在於 Package, Program Memory Type, Core Architecture, Operating Temperature, ADC.
PIC18C601T-I/PT
✅ 直接替換聯絡詢價
查看資料表 →PIC18C801-I/PT
✅ 直接替換聯絡詢價
查看資料表 →PIC18F8720-I/PT
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
PIC18F8722-I/PT
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →PIC18C601-I/PT 最大額定值與電氣特性
| Product Family | PIC18C |
| Core Architecture | PIC 8-bit RISC |
| Program Memory Type | ROMless (external memory bus) |
| Program Memory Size | 0 (external up to 2 Mbytes) |
| RAM Size | 1.5 KB (1536 bytes) |
| Maximum CPU Speed | 25 MHz (6.25 MIPS) |
| Supply Voltage (VDD) | 4.2 V to 5.5 V |
| Number of I/O Pins | 26 |
| External Memory Bus Width | 16-bit / 8-bit selectable |
| Instruction Set Size | 77 single-word instructions |
| Stack Depth | 31 levels |
| 工作溫度 | -40 C to +85 C (Industrial) |
| 封裝 | 64-pin TQFP (10x10 mm) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| Oscillator Type | External |
PIC18C601-I/PT 腳位配置
| 腳位 1 | NC — Not connected (per datasheet) |
| 腳位 2 | RA0/AN0 — PORTA bit 0 / analog input 0 |
| 腳位 3 | RA1/AN1 — PORTA bit 1 / analog input 1 |
| 腳位 4 | RA2/AN2 — PORTA bit 2 / analog input 2 |
| 腳位 5 | RA3/AN3/VREF+ — PORTA bit 3 / analog input 3 / VREF+ |
| 腳位 6 | RA4/T0CKI — PORTA bit 4 / Timer0 clock input |
| 腳位 7 | RA5/AN4/SS — PORTA bit 5 / analog input 4 / SPI slave select |
| 腳位 8 | VSS — Ground |
| 腳位 9 | OSC1/CLKIN — Oscillator input / external clock in |
| 腳位 10 | OSC2/CLKOUT — Oscillator output / clock out |
| 腳位 11 | RC0/T1OSO/T1CKI — PORTC bit 0 / Timer1 I/O |
| 腳位 12 | RC1/T1OSI/CCP2 — PORTC bit 1 / Timer1 oscillator / CCP2 |
| 腳位 13 | RC2/CCP1 — PORTC bit 2 / CCP1 |
| 腳位 14 | RC3/SCK/SCL — PORTC bit 3 / SPI SCK / I2C SCL |
| 腳位 15 | RD0/AD0 — PORTD bit 0 / external address/data bit 0 |
| 腳位 16 | RD1/AD1 — PORTD bit 1 / external address/data bit 1 |
| 腳位 17 | RD2/AD2 — PORTD bit 2 / external address/data bit 2 |
| 腳位 18 | RD3/AD3 — PORTD bit 3 / external address/data bit 3 |
| 腳位 19 | RD4/AD4 — PORTD bit 4 / external address/data bit 4 |
| 腳位 20 | RD5/AD5 — PORTD bit 5 / external address/data bit 5 |
| 腳位 21 | RD6/AD6 — PORTD bit 6 / external address/data bit 6 |
| 腳位 22 | RD7/AD7 — PORTD bit 7 / external address/data bit 7 |
| 腳位 23 | VSS — Ground |
| 腳位 24 | VDD — Positive supply (4.2-5.5 V) |
| 腳位 25 | RB0/INT0 — PORTB bit 0 / external interrupt 0 |
| 腳位 26 | RB1/INT1 — PORTB bit 1 / external interrupt 1 |
| 腳位 27 | RB2/INT2 — PORTB bit 2 / external interrupt 2 |
| 腳位 28 | RB3/INT3 — PORTB bit 3 / external interrupt 3 |
| 腳位 29 | RB4 — PORTB bit 4 |
| 腳位 30 | RB5 — PORTB bit 5 |
| 腳位 31 | RB6/PGC — PORTB bit 6 / ICSP clock |
| 腳位 32 | RB7/PGD — PORTB bit 7 / ICSP data |
| 腳位 33 | MCLR/VPP — Master clear reset / programming voltage |
| 腳位 34 | RE0/AD8 — PORTE bit 0 / external address/data bit 8 |
| 腳位 35 | RE1/AD9 — PORTE bit 1 / external address/data bit 9 |
| 腳位 36 | RE2/AD10 — PORTE bit 2 / external address/data bit 10 |
| 腳位 37 | RE3/AD11 — PORTE bit 3 / external address/data bit 11 |
| 腳位 38 | RE4/AD12 — PORTE bit 4 / external address/data bit 12 |
| 腳位 39 | RE5/AD13 — PORTE bit 5 / external address/data bit 13 |
| 腳位 40 | RE6/AD14 — PORTE bit 6 / external address/data bit 14 |
| 腳位 41 | RE7/AD15 — PORTE bit 7 / external address/data bit 15 |
| 腳位 42 | VSS — Ground |
| 腳位 43 | VDD — Positive supply (4.2-5.5 V) |
| 腳位 44 | ALE — Address latch enable for external memory bus |
| 腳位 45 | OE — Output enable for external memory |
| 腳位 46 | WR — Write enable for external memory |
| 腳位 47 | RC4/SDI/SDA — PORTC bit 4 / SPI SDI / I2C SDA |
| 腳位 48 | RC5/SDO — PORTC bit 5 / SPI SDO |
| 腳位 49 | RC6/TX/CK — PORTC bit 6 / UART TX / clock |
| 腳位 50 | RC7/RX/DT — PORTC bit 7 / UART RX / data |
| 腳位 51 | VSS — Ground |
| 腳位 52 | NC — Not connected (per datasheet) |
| 腳位 53 | NC — Not connected (per datasheet) |
| 腳位 54 | NC — Not connected (per datasheet) |
| 腳位 55 | NC — Not connected (per datasheet) |
| 腳位 56 | NC — Not connected (per datasheet) |
| 腳位 57 | NC — Not connected (per datasheet) |
| 腳位 58 | NC — Not connected (per datasheet) |
| 腳位 59 | NC — Not connected (per datasheet) |
| 腳位 60 | NC — Not connected (per datasheet) |
| 腳位 61 | NC — Not connected (per datasheet) |
| 腳位 62 | NC — Not connected (per datasheet) |
| 腳位 63 | NC — Not connected (per datasheet) |
| 腳位 64 | NC — Not connected (per datasheet) |
典型應用
PIC18C601-I/PT 適用於 6 應用s: Industrial Control Systems, Automotive Body Electronics, Point-of-Sale Terminals, Consumer Appliances, Legacy Migration from PIC16C5X/PIC12CXXX, Test and Measurement Equipment.
Industrial Control Systems
The PIC18C601-I/PT fits industrial control because its 25 MHz CPU and 1.5 KB RAM comfortably handle PID loops, sensor scanning, and relay sequencing. With 26 digital I/O plus the external memory bus, it can drive multi-axis stepper drivers and 4-20 mA loops while keeping the firmware in field-replaceable external EPROM. The 4.2-5.5 V supply range tolerates 24 V-derived industrial rails, and the -40C to +85C industrial grade suits factory cabinets. Placed on the main controller PCB between the I/O connector and the power supply, the C601 reduces BOM cost versus Flash parts and lets the factory swap firmware by replacing a chip.
推薦
Automotive Body Electronics
The PIC18C601-I/PT is suited for body-electronics modules such as seat controllers, window lifters, and lighting timers. Its external memory bus lets the OEM store large CAN/LIN lookup tables in external Flash, while the 77-instruction RISC core executes state machines within 160 ns per instruction. The 26 I/O pins support H-bridge drivers, Hall sensors, and indicator LEDs without external muxing. The part operates across -40C to +85C, matching SAE automotive body temperature profiles. Although automotive designs today favor PIC18F-Q1 parts, legacy PIC18C601 designs remain in service fleets and benefit from documented pinouts.
推薦
Point-of-Sale Terminals
The PIC18C601-I/PT serves POS terminals that need an external memory bus for font tables, encryption keys, or modular firmware images stored in removable Flash. Its 25 MHz core drives character LCDs, keypad scanning, and serial peripherals while leaving headroom for modular firmware upgrades. The 1.5 KB RAM holds transaction buffers and UART FIFOs. Placed between the display driver and the printer interface, it reduces unit cost compared with Flash-based MCUs because the same firmware image can serve multiple product variants by swapping external memory chips.
推薦
Consumer Appliances
The PIC18C601-I/PT is well-matched to white-goods controllers in washing machines, dishwashers, and microwave ovens where the BOM must be minimized. The external memory bus lets the manufacturer keep program code on a low-cost EPROM next to the MCU, and the 26 I/O pins drive triac outputs, keypads, and seven-segment displays directly. The wide 4.2-5.5 V supply range tolerates rectified mains rails, and the -40C to +85C grade covers unheated appliance enclosures. A typical implementation places the C601 between the mains zero-cross detector and the relay/triac driver stage, executing timed motor and heater sequences within 160 ns per instruction.
推薦
Legacy Migration from PIC16C5X/PIC12CXXX
The PIC18C601-I/PT is the recommended Microchip migration path for designers carrying forward PIC16C5X and PIC12CXXX code. Its 77-instruction RISC core is upwards compatible with those older families, while the external memory bus removes the program-size ceiling that limited earlier PIC parts to 1-2 KB. Drop-in 64-pin TQFP packages allow existing PCBs to be reused with minor firmware porting. The 25 MHz CPU delivers roughly 4x the throughput of PIC16C5X at 20 MHz, accelerating control loops without forcing a full board redesign. It is typically placed as the system MCU on legacy adapter boards bridging older code to new peripherals.
推薦
Test and Measurement Equipment
The PIC18C601-I/PT fits mid-range test and measurement front-ends where its external memory bus stores calibration constants and waveform tables. The 25 MHz core sequences ADC conversions, manages front-panel keypads, and drives character displays while leaving enough headroom for serial I/O with the host PC. The 1.5 KB RAM buffers sample streams before DMA or interrupt-driven transfers. Designers benefit from the part's documented 64-pin TQFP pinout and Microchip's extensive PIC18 assembly/C toolchain support, which simplifies porting of legacy calibration firmware to modern production testers.
推薦
推薦產品摘要
工程參考資料，適用於 PIC18C601-I/PT — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | PIC18C601T-I/PT | PIC18C801-I/PT | PIC18F8720-I/PT | PIC18F8722-I/PT |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-pin TQFP (10x10 mm) | 64-pin TQFP (10x10 mm) - same | 64-pin TQFP - same | 64-pin TQFP - same | 64-pin TQFP - same |
| Program Memory | 0 (ROMless, external up to 2 MB) | 0 (ROMless, external up to 2 MB) | 0 (ROMless, extended external) | 128 KB Flash on-chip | 256 KB Flash on-chip |
| RAM Size | 1.5 KB | 1.5 KB | 1.5 KB | 3.84 KB | 3.84 KB |
| Maximum CPU Speed | 25 MHz (6.25 MIPS) | 25 MHz (6.25 MIPS) | 25 MHz (6.25 MIPS) | 25 MHz | 40 MHz |
| Number of I/O | 26 | 26 | 26 | 70 | 70 |
| Supply Voltage | 4.2 V to 5.5 V | 4.2 V to 5.5 V | 4.2 V to 5.5 V | 4.2 V to 5.5 V | 4.2 V to 5.5 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Active | Active |
| Internal Memory Migration | N/A (ROMless) | N/A (ROMless) | N/A (ROMless) | Firmware port required | Firmware port required |
主要差異化特點
- ROMless architecture with 2 MB external program memory addressing (對比PIC18F8720-I/PT)
- Documented upward compatibility from PIC16C5X/PIC12CXXX (對比PIC18F8722-I/PT)
- Lower unit cost when paired with commodity external EPROM (對比PIC18F8720-I/PT)
設計說明
Place a 100 nF ceramic decoupling capacitor plus a 10 uF bulk capacitor within 25 mm of each VDD pin (pins 24 and 43) and a 100 nF cap at each VSS pin. The 5 V supply must remain within 4.2 V to 5.5 V to meet the 40 ns external memory cycle timing. Brown-out detector configuration should be enabled in CONFIG to prevent code corruption during power dips.
Route the external memory bus (AD0-AD15, ALE, OE, WR) with matched trace lengths and a maximum stub length of 12 mm to avoid timing violations at 25 MHz. Place external EPROM/Flash as close as possible to the AD bus pins on the same PCB layer to minimize capacitive loading. Per Microchip's PIC18C601/801 datasheet, the bus can be configured for multiplexed or separate address/data, and trace impedance should be controlled when bus length exceeds 50 mm.
Do not assume on-chip program memory exists: PIC18C601 is ROMless and requires an external EPROM/Flash/SRAM. When migrating from a PIC18C601 design to a PIC18F8720 or PIC18F8722, the firmware must be re-targeted for the new Flash memory map; do not assume object code compatibility. Also note that the I suffix indicates the industrial temperature grade (-40C to +85C), not RoHS or other compliance flags.
Estimated: at 25 MHz and 5 V VDD with all 26 I/O pins switching at 10 MHz, typical power dissipation is approximately 60 mW (I_DD roughly 12 mA). The 64-pin TQFP package has a junction-to-ambient thermal resistance of approximately 50 C/W on a standard 4-layer JEDEC test board, giving a temperature rise of only 3 C above ambient - no heatsink is required for normal operation.
合規資訊
RoHS compliance per Microchip product page. The PIC18C601 family is not AEC-Q100 qualified for automotive designs. Halogen-free status not explicitly listed in verified web data - marked unknown. The I suffix denotes industrial temperature grade, not a compliance classification.
