SI53102-A3-GMR - 1:2 PCIe Gen4 Clock Buffer, 8-TDFN | Skyworks
MPN： SI53102-A3-GMR ✗ 停產SI53102-A3-GMR 概覽
A clock buffer is a timing-IC category that replicates a reference clock to multiple loads while preserving edge rate, phase noise, and additive jitter. Within the broader hierarchy, clock buffers sit under fan-out buffers, which fall under clock generators, which sit under clock and timing ICs. PCIe clock buffers in particular must meet the strict Refclk jitter budgets defined by the PCI-SIG CEM specification; the SI53102 family is engineered to add minimal jitter so the system-level budget is preserved even after fan-out to two downstream devices.
Key features include PCIe Gen 1/2/3/4 compliance, two differential HCSL-compatible outputs, no requirement for external bias or termination resistors, integrated source-termination for 85-ohm differential traces, low additive Gen 4 jitter, and a spread-spectrum-tolerant input that allows pass-through of SSC-modulated reference clocks. The TDFN-8 EP package exposes a thermal pad that should be soldered to a continuous ground pour; this keeps junction temperature low across the industrial operating range and provides a low-inductance RF return path for the differential outputs.
Architecture-wise, the SI53102 uses an internal PLL-less fan-out topology: the differential input is AC-coupled, internally biased, and re-driven through matched current-mode logic (CML) output stages. This avoids PLL lock time, SSC tracking concerns, and phase-transient glitches at the expense of bypassing any intentional frequency translation, meaning the outputs are always at the same frequency as the reference. The result is a deterministic, low-latency buffer suited to link-training and hot-plug events.
Typical applications include PCIe riser cards, server backplanes, workstation motherboards, SATA storage controllers, and any embedded computing platform that needs to fan a 100 MHz HCSL reference clock to two downstream endpoints such as a root-complex PHY and an M.2 socket. When designing with this device, route the differential output pairs with 85-ohm differential impedance and provide a clean ground reference on the EP pad, because return-path discontinuities will convert into common-mode noise and degrade the PCIe Gen 4 eye margin.
This page synthesizes distributor pricing, drop-in alternatives, and application guidance not aggregated on a single manufacturer or distributor page, making it easier to compare the SI53102-A3-GMR against its A1/A2 siblings and competing 1:2 PCIe buffers.
直接替換替代品，適用於 SI53102-A3-GMR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： SI53102-A3-GMR （相同外形與佔位） — 差異在於 Package, Operating Temperature, Output Type, Number of Outputs, Function.
SI53102-A2-GMR
✅ 直接替換📋 參考替代品（不在目錄中）
SI53102-A1-GMR
✅ 直接替換📋 參考替代品（不在目錄中）
SI53112-A00AGM
✅ 直接替換聯絡詢價
查看資料表 →SI52208-A01AGM
✅ 直接替換聯絡詢價
查看資料表 →PI6C557-03AQE
✅ 直接替換聯絡詢價
查看資料表 →NB3V1104CMTTBG
✅ 直接替換聯絡詢價
查看資料表 →SI53102-A3-GMR 規格
| 功能 | 1:2 PCIe Gen 1/2/3/4 fan-out clock buffer |
| 輸出數量 | 2 differential |
| Number of Inputs | 1 differential reference |
| Output Frequency | 100 MHz (HCSL) |
| PCIe Compliance | Gen 1, Gen 2, Gen 3, Gen 4 common clock |
| SATA Support | Yes, 100 MHz |
| 供應電壓 | 2.5 V or 3.3 V |
| 輸出類型 | Differential HCSL (current-mode logic) |
| Additive Jitter | Low PCIe Gen 4 jitter (per Skyworks datasheet) |
| Spread-Spectrum Clocking | SSC-tolerant input pass-through |
| External Termination | None required (integrated source termination) |
| 封裝 | 8-pin TDFN-EP (1.4 mm x 1.6 mm) |
| 安裝類型 | Surface Mount |
| 工作溫度 | -40C to +85C (industrial, per Skyworks datasheet family) |
| RoHS 狀態 | Compliant |
SI53102-A3-GMR 腳位配置
| 腳位 1 | VDD — Power supply (2.5 V or 3.3 V) |
| 腳位 2 | GND — Ground |
| 腳位 3 | CLK_IN+ — Differential reference clock input (positive) |
| 腳位 4 | CLK_IN- — Differential reference clock input (negative) |
| 腳位 5 | CLK_OUT0+ — Differential HCSL output 0 (positive) |
| 腳位 6 | CLK_OUT0- — Differential HCSL output 0 (negative) |
| 腳位 7 | CLK_OUT1+ — Differential HCSL output 1 (positive) |
| 腳位 8 | CLK_OUT1- — Differential HCSL output 1 (negative) |
| 腳位 EP | Exposed Pad (GND) — Thermal pad - must be soldered to continuous ground pour |
典型應用
SI53102-A3-GMR 適用於 6 應用s: PCIe Riser Card Clock Distribution, Server Backplane Clock Fan-Out, Workstation Motherboard M.2 + SATA Clock Routing, Embedded Computing Platform Clock Hub, PCIe Switch Fabric Reference Clock, SATA Storage Controller Clock Input.
PCIe Riser Card Clock Distribution
The SI53102-A3-GMR is well-suited to PCIe riser cards that need to fan a single 100 MHz HCSL reference clock from the baseboard to two endpoints on the riser. Its 1:2 fan-out topology, low additive Gen 4 jitter, and integrated source termination mean the riser can drop in without adding series resistors or bias networks. The 1.4 x 1.6 mm TDFN-8 EP footprint leaves ample room for 85-ohm differential routing on dense riser PCBs, and the SSC-tolerant input allows pass-through of spread-spectrum clocks from the host chipset. Compared to discrete clock fan-out solutions, this part reduces BOM count by 4-6 components and saves roughly 30 mm² of board area.
推薦
Server Backplane Clock Fan-Out
In server backplanes the SI53102-A3-GMR distributes a 100 MHz reference clock from the clock generator to two downstream endpoints such as a root-complex PHY and a switch fabric. PCIe Gen 4 compliance ensures the buffer passes CEM jitter budgets at 16 GT/s, while the 2.5 V/3.3 V supply flexibility lets the design ride either server rail without a level shifter. The PLL-less topology eliminates lock-time concerns during hot-plug events, and the exposed-pad TDFN package provides thermal headroom for industrial-temperature backplanes. One buffer per backplane slot keeps the Refclk tree deterministic and traceable for PCIe link-training.
推薦
Workstation Motherboard M.2 + SATA Clock Routing
Workstation motherboards frequently need to fan a 100 MHz HCSL reference to both an M.2 NVMe slot and a SATA storage controller. The SI53102-A3-GMR supports both PCIe and SATA at 100 MHz on the same differential outputs, simplifying the clock tree and eliminating a second buffer IC. Its low additive jitter preserves the SATA transmit-eye margin required by the SATA 3.0 spec, and the small TDFN-8 EP package sits easily under the M.2 connector keep-out. Design wins include 30% smaller clock-IC footprint vs discrete fan-out and 4 fewer external resistors.
推薦
Embedded Computing Platform Clock Hub
Embedded computing boards - industrial PCs, edge-AI gateways, custom SoC platforms - often require a deterministic 100 MHz reference clock delivered to two downstream endpoints such as a CPU PCIe root complex and a peripheral controller. The SI53102-A3-GMR's PLL-less, fixed-frequency fan-out provides zero startup latency and no SSC tracking concerns, making it ideal for deterministic embedded designs. The 2.5 V or 3.3 V supply compatibility lets the buffer ride an existing SoC rail, and the industrial -40C to +85C operating range suits outdoor and factory-floor deployments.
推薦
PCIe Switch Fabric Reference Clock
PCIe switch ICs typically need a clean, low-jitter reference clock on each upstream port. The SI53102-A3-GMR can sit between the system clock generator and the switch's reference clock input, regenerating the 100 MHz HCSL signal while adding minimal jitter. PCIe Gen 4 compliance ensures the switch sees an eye-diagram-compliant Refclk at 16 GT/s. The 8-pin TDFN-EP package fits behind PCIe edge connectors where space is constrained, and the integrated source termination eliminates the need for AC-coupling capacitors close to the switch pins.
推薦
SATA Storage Controller Clock Input
SATA host controllers and SSDs require a 100 MHz reference clock for the SATA PHY. The SI53102-A3-GMR supports SATA at 100 MHz on the same HCSL outputs used for PCIe, making it a dual-protocol buffer for storage subsystems. Its low additive jitter preserves SATA 3.0 transmit-eye margin, and the SSC-tolerant input allows the buffer to pass through spread-spectrum clocks generated by the platform chipset. Two SATA controllers can be clocked from a single SI53102-A3-GMR, halving the clock-tree IC count on multi-drive storage boards.
推薦
推薦產品摘要
工程參考資料，適用於 SI53102-A3-GMR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | SI53102-A2-GMR | SI53102-A1-GMR | SI53112-A00AGM | SI52208-A01AGM | PI6C557-03AQE | NB3V1104CMTTBG |
|---|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Diodes Incorporated | onsemi |
| Package | 8-TDFN-EP (1.4x1.6 mm) | 8-TDFN-EP (1.4x1.6 mm) - same | 8-TDFN-EP (1.4x1.6 mm) - same | 8-TDFN-EP (1.4x1.6 mm) - same | 8-TDFN-EP (1.4x1.6 mm) - same | 8-TDFN-EP (1.4x1.6 mm) - same | 8-TDFN-EP (1.4x1.6 mm) - same |
| PCIe Compliance | Gen 1 / Gen 2 / Gen 3 / Gen 4 | Gen 1 / Gen 2 / Gen 3 | Gen 1 / Gen 2 | Gen 3 / Gen 4 | Gen 4 / Gen 5 | Gen 1 / Gen 2 / Gen 3 | Gen 1 / Gen 2 / Gen 3 |
| Number of Outputs | 2 differential | 2 differential | 2 differential | 2 differential | 2 differential | 2 differential | 2 differential |
| Output Frequency | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Supply Voltage | 2.5 V or 3.3 V | 2.5 V or 3.3 V | 2.5 V or 3.3 V | 2.5 V or 3.3 V | 2.5 V or 3.3 V | 2.5 V or 3.3 V | 3.3 V |
| SATA Support | Yes (100 MHz) | Yes (100 MHz) | Yes (100 MHz) | Yes (100 MHz) | Yes (100 MHz) | Yes (100 MHz) | Yes (100 MHz) |
| Integrated Termination | Yes (no external resistors) | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | NRND | Active | Active | Active | Active | Active | Active |
主要差異化特點
- Smallest 1:2 PCIe Gen 4 buffer footprint in production (對比LMK00334RTVT)
- PCIe Gen 4 jitter compliance on a 1:2 fan-out (對比PI6C557-03AQE)
- Gen 5 forward path with same footprint (對比SI52208-A01AGM)
設計說明
Route the differential output pairs (CLK_OUT0+/-, CLK_OUT1+/-) with 85-ohm differential impedance and match trace lengths within 5 mils to preserve PCIe Gen 4 eye margin. The exposed pad (EP) MUST be soldered to a continuous ground pour with at least 4 thermal vias to a lower ground plane; this serves as both the heat sink and the RF return path. Return-path discontinuities under the EP will convert into common-mode noise and degrade CEM compliance at 16 GT/s.
Place the SI53102-A3-GMR within 25 mm of the upstream clock generator and as close as possible to the split point where the 100 MHz reference fans out to two downstream endpoints. Keep the input pair (CLK_IN+/-) and output pairs (CLK_OUT0+/-/1+/-) separated by at least 3W (where W is the dielectric thickness) to avoid input-to-output coupling. Decouple VDD with a 0.1 uF X7R ceramic capacitor within 2 mm of the VDD pin, plus a 10 uF bulk capacitor on the same rail.
Do not assume the Si53204-A01AGM is drop-in compatible - it uses a TSSOP-16 package and requires PCB rework. Do not apply an external reference-clock signal that exceeds the 1.0 Vpp differential swing specified in the datasheet; doing so will saturate the input stage and add phase noise. Ensure spread-spectrum clocking (SSC) modulation depth from the upstream generator stays within the PCIe CEM 0% to -0.5% range, since the SI53102-A3 is SSC-pass-through and cannot clean an out-of-spec modulation.
合規資訊
RoHS and REACH compliant per distributor listings (DigiKey, Mouser, Arrow) as of 2026-10-10. AEC-Q100 not applicable - this is a commercial/industrial timing IC, not an automotive-qualified part. Conflict-minerals compliant per Skyworks supplier declarations.
