10AX066K2F40I1SG vs 10AX066K1F40I1SG 对比
详细并排对比 10AX066K2F40I1SG 出自 Intel 和 10AX066K1F40I1SG 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
10AX066K1F40I1SG - Arria 10 GX 660K LE FPGA, 1517-BGA, Industrial | Intel / Altera
10AX066K1F40I1SG ✓ 量产中规格对比
| 参数 | 10AX066K2F40I1SG | 10AX066K1F40I1SG |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $3,395.00 | $2,820.00 |
| Family | Arria 10 GX | Intel Arria 10 GX |
| Logic Elements (LE) | 660,000 | 660,000 |
| Embedded Memory Bits | 49,610,752 (approx. 49.6 Mbit) | — |
| User I/O Count | 696 | — |
| 封装 | 1517-BBGA, FCBGA (Flip-Chip BGA) | 1517-BBGA / FCBGA, 40 x 40 mm, 1.0 mm pitch |
| Package Size | 40 mm x 40 mm | — |
| Ball Pitch | [DATA_NEEDED: ball pitch] | — |
| Process Technology | 20 nm | — |
| Transceiver Data Rate (max) | 17.4 Gbps | — |
| Hard Memory Controller | Yes (DDR3/DDR4, QDR IV, RLDRAM 3) | — |
| PCIe Hard IP | PCI Express Gen3 x8 | — |
| Hard Processor System | Dual ARM Cortex-A9 MPCore | — |
| DSP Blocks | Hardened floating-point DSP blocks | 696 |
| DSP Performance | Up to 1.5 TFLOPs (floating point) | — |
| Configuration Modes | AS, PS, JTAG, FPP | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT] | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| RoHS 状态 | Compliant (per manufacturer) | Compliant |
| Embedded Memory (bits) | — | 49,610,752 |
| Temperature Grade | — | Industrial (I) |
| Speed Grade | — | 1 (slowest industrial, lowest power) |
| Process Node | — | TSMC 20 nm |
| 工作结温 | — | -40C to +100C |
| Transceivers | — | Up to 24 channels (GX) |
| Maximum Transceiver Data Rate | — | 17.4 Gbps (per Arria 10 family datasheet) |
| Hard Memory Controllers | — | Yes (DDR4 / DDR3 / QDR-IV / RLDRAM3) |
| Hard PCIe IP | — | PCIe Gen3 x8 hard IP |
| User I/O Banks | — | [DATA_NEEDED: user I/O bank count and total GPIO] |
| Configuration Schemes | — | AS, PS, JTAG, FPP |
| MSL 等级 | — | MSL3 (per JEDEC J-STD-020 for FCBGA) |